JPS61166239A - Timing recovery circuit - Google Patents

Abstract

PURPOSE:To prevent increase in data error due to scrambling even when an error takes place by applying timing recovery during training period and fixing a timing period at the end of training in a data transmission MODEM. CONSTITUTION:When a timing set switch (SW) 28 reaches +1, an output (T3) of an AND circuit (AND1) 26 and an output (T4) of a timing set switch (SW) 28 are ANDed by an AND circuit (AND2) 29, and the result (T5) is fed to a counter (counter 1) 30 and an AND circuit (AND4) 31. The counter (counter 1) 30 counts the leading of an input (IN) and the count number of the counter (counter 1) 30 and a training symbol number stored in a register (REG3) 32 are compared with an AND circuit (AND3) 33. When the both are equal, the output of the AND circuit (AND3) 33 reaches +1 and +1 is held in the output of the AND circuit (AND3) 33.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a timing regeneration circuit, and more specifically, it is suitably applied to a data transmission modem used in mobile communications such as a car phone, and is suitable for use in digital The present invention relates to a timing recovery circuit configured using a circuit or digital signal processing technology.

(Prior art) Conventionally, many of these types of circuits were constructed from analog circuits, and even when digital circuits or digital signal processing technology was used, basically the analog circuits were replaced with the circuit technology described above. It was common. An example of this is described in Oki Research and Development Vol. 1.43 No. 2, pages 11 to 20. The timing recovery circuit disclosed in the above document will be explained below.

This conventional timing recovery circuit is composed of a timing extraction circuit and a timing A20 circuit.

A block diagram of the timing extraction circuit is shown in FIG. 5, and a block diagram of the timing A20 circuit is shown in FIG.

As shown in FIG. 5, the timing extraction circuit includes high-pass filters (HPF) 1, 7 and full-wave rectifier circuits (ABS) 2, 8.
, a summing amplifier 3, a bandpass filter (BPF) 4, a high level slicer 5, and a low level slicer 6. The high-pass filter 1 and the aftermath rectifier circuit 2 are for in-phase demodulated baseband signals, and the high-pass filter 7 and the aftermath rectifier circuit 8 are for orthogonal demodulated baseband signals.

To describe the operation of the timing extraction circuit, first, the high-pass filter 1 extracts the symbol period component contained in the in-phase demodulated baseband signal through the symbol period component. The extracted symbol period component passes through the aftermath rectifier circuit 2, and a double wave component is created. The created second harmonic component is sent to the summing amplifier 3. Similarly, the high-pass eyelid filter 7 extracts the symbol period component contained in the orthogonal demodulated baseband signal through the symbol period component.6 The extracted symbol period component passes through the aftereffect rectifier circuit 8, and a second harmonic component is created. Ru.

This second harmonic component is also sent to the summing amplifier 3. In the summing amplifier 3, the sum of the sent second harmonic components is calculated, and the output thereof is supplied to a bandpass filter 4, where a timing signal is extracted. The extracted timing signal is sent to a high level slicer 5 and a low level slicer 6, and the signal T is sliced at a zero level and a high level above a certain level.
IM-0 and TIM-H are each created. The phase of TIM-0 when TIM-H is obtained is then used as a reliable timing phase in the timing A20 circuit.

On the other hand, the timing A20 circuit, as shown in FIG.
First flip-flop 11, phase shifter 12, differentiator circuit 1
3. Second flip-flop 14, first counter 15
, gate 16, control circuit 17, and second counter 18
It consists of

To describe the operation of the above timing A20 circuit, the first flip-flop 11 has TIM-H input.
Extract the IM-0 manual conversion point.

The phase shifter 12 is composed of a monostable multi-vibrator and sets the initial pull-in phase. Differentiating circuit 13 differentiates the rising point of the output of phase shifter 12 with respect to the clock. The second flip-flop 14 is set by this differential pulse,
The second counter 18 is reset at the rising edge of the reproduction timing. Therefore, the phase difference is output from the second flip-flop 14, the first counter 15 counts this phase difference, and when the phase difference is large, the gate 1B is opened and the output of the differentiating circuit 13 is passed through. Game if small)
1B is closed to prevent the output of the differential circuit 13 from passing through. The control circuit 17 is a differentiating circuit 13. The output of A
Receives the PC output, compares the lead and lag of the two phases, and performs advance/delay control by inserting and removing clock pulses in the frequency divider circuit, so that the APC output phase follows the differentiating circuit output phase. will be done. Note that this circuit includes a scrambler circuit (not shown) on the transmitting side to ensure carrier and timing synchronization.

(Problem to be solved by the invention) However, in a data transmission modem using a conventional timing recovery circuit, it is necessary to provide a scrambler circuit on the transmitting side, and this scrambler circuit increases data errors. This has the disadvantage that the modem for data transmission is prone to errors.

Therefore, the present invention was made in order to solve the problems of the prior art, and an object thereof is to provide a timing recovery circuit that is constructed using a digital circuit or digital signal processing technology and has fewer data errors. shall be.

(Means for Solving the Problems) In order to solve the problems of the prior art described above, the first invention is comprised of the following first to fifth means.

The first means receives a timing signal extracted from a received signal, performs initial phase adjustment of the timing signal using a training signal, and determines whether to start training. This first means is composed of, for example, a plurality of determination circuits and timing set switches. The second means is
It receives the output of the first means and counts the number of symbols during training, and is composed of a counter. The third means determines whether training is complete based on the output of the second means. This training completion determination is made, for example, based on whether the symbol count number output from the second means has reached a predetermined count number. The fourth means stores and holds timing cycle data at the end of training. The fifth means generates a timing reproduction output based on the information from the first means, and after the training ends, outputs a timing reproduction output of a fixed timing period by comparing the content with the fourth means. .

Further, the second invention includes a sixth means in addition to the first to fifth means of the first invention. This sixth means resets the fifth means when a timing reproduction output equal to or greater than a certain fixed value is obtained.

(Operations) First, according to the first invention, the following operations are performed. That is, the first and fifth means perform timing recovery during the training period using the timing signal extracted from the received signal, and the first means performs initial phase alignment of the timing signal and determination of the start of training based on the training signal. do. On the other hand, according to the second and third means, an operation for determining the end of training is performed. When the fourth means receives the information of the end of the training game from the third means, it stores and holds the timing cycle data at that time.

The fifth means outputs a timing reproduction output having a fixed timing period after the training is completed.

Therefore, there is no need to provide a scrambling circuit on the transmitting side, and the problems of the prior art described above can be solved.

Further, in the second invention, in addition to the effect of the first invention, when a timing reproduction output larger than a certain value is obtained even other than during training, the sixth means transmits the timing signal to a previous timing. It works to give priority to signals.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a circuit diagram showing a timing regeneration circuit of this embodiment, and FIG. 2 is a time chart showing an example of signal timing of each part of the circuit. In FIG. 1, 21 is an input terminal, 22 is a register (REGl), 23 is a register (, REG2), 24 is a judgment circuit (judgment 1), 25 is a judgment circuit (judgment 2), and 2B is an AND circuit (ANDl). ),
27 is a judgment circuit (judgment 3), 28 is a timing set switch (SW), 29 is an AND circuit (AND2), 30
is a counter (counter 1), 31 is an AND circuit (AND
4), 32 is a register (REG3), 33 is an AND circuit (AND3), 34 is an inverter, 35 is an AND circuit (AND5), 3B is an OR circuit (OR), 3? is an inverter, 38 is a counter (counter 2), 38 is a register (REG4), 40 is an AND circuit (AND6),
41 is an AND circuit (AND8), 42 is an AND circuit (
AND7), 43 is an AND circuit (AND9), 44
45 is a timing output terminal, and 45 is a clock input terminal. Furthermore, in the time chart of FIG. 2, CK is the clock, T1 is the output of the determination circuit (determination 1) 24, T2 is the output of the determination circuit (determination 2) 25, and T3 is the AND circuit (AND
I) 2B output, T4 is the timing set switch (S
W)28 output, T5 is an AND circuit (AND2)
29 output, T6 is the output of the inverter 34, Tl is the output of the AND circuit (AND4) 31, T8
is the output of the AND circuit (AND5) 35, T9 is the output of the AND circuit (AND9) 43, and TIO is the inverter 37.
Tll indicates the output of the AND circuit (AND6) 40.

Next, the operation will be explained. The input terminal 21 has a digital timing extraction circuit B having the circuit configuration shown in FIG.
9. PF output is 6 times the baud rate period. [Input for each fkHz sample. The BPF data input to the input terminal 21 is a sample clock (CK).

The data is stored in the register (REGI) 22 where data is set at the rising edge of FIG. 2(a). Register (REG)
The data stored in I) 22 is similarly stored in the register (R
EG2) 23. Register (REGI) 22
and the data stored in the register (REG2) 23 are sent to the judgment circuit (judgment 1) 24 and the judgment circuit (judgment 2), respectively.
) 25 with a predetermined level. The judgment circuit (judgment l) 24 outputs +1 when the value of the register (REGI) 22 is on the negative side of the negative constant level, while the judgment circuit (judgment 2) 25 outputs +1 when the value of the register (REG2) is positive. If it is on the positive side of a certain level, +1 is output. The outputs (Tl and T
2. FIG. 2(b) and (C)) are AND circuits (AND
1) 2B is ANDed, AND circuit (ANDI
) 2B output (T3; FIG. 2(d)) is +1, the determination circuit (determination 3) 27 operates and level determination is performed. When the value of the register (REGI) 22 exceeds a certain value, the timing set switch (SW) 28 becomes +1,
The data is held by a timing set switch (SW) 28 until a training start command is received. Note that training here refers to establishing the operation of the receiving section of the modem on the other side, and the training signal refers to a predetermined fixed code string for this purpose.

When the timing set switch (SW) 2B becomes +1, the AND circuit (AND2) 29 outputs the output (T3) of the AND circuit (ANDI) 28 and the output (T4) of the timing set switch (SW) 28; Fig. 2 (e). ) is A
ND is taken, and the result (T5; Fig. 2 (f)) is sent to the counter (counter l) 30 and the AND circuit (AND4).
Sent to 31. The counter (counter 1) 30 counts the rising edge of the input (IN), and the count number of the counter (counter l) 30 and the register (REG3) 3
An AND circuit (AND3) 33 compares the value of the number of training symbols stored in 2 and 33. If the two values are equal, the output of the AND circuit (AND3) 33 becomes +1, and the counter (counter 1) 30 holds the value until a training start command is received.
The output of the ND circuit (AND3) 33 is also held at the value of +1. The AND circuit (AND4) 31 includes an AND circuit (
AND2 )29 output (T5) and the AND circuit (AN
The output of D3) 33 is inverted by the inverter 34 (T6; FIG. 2(g)). AND circuit (AND
4) 31 detects the zero level cross point of the rising edge of timing extraction until the f value of the counter (counter l) 30 becomes equal to the register (REG3) 32. AN
Output of D circuit (AND4) 31 (Tl: Fig. 2 (h)
) enters one input of the AND circuit (AND5) 35. The other input of the AND circuit (AND5) 35 has 9
．． An 8kHz sample clock (CK) is input. AN
Output of D circuit (AND5) 35 (T8; Figure 2 (i))
is supplied to the OR circuit (OR) 3B, where the output of the AND circuit (AND9) 43 (T9; Fig. 2 (j)) and O
R is taken and the resulting output is sent to the cariter (counter 2
) 38 and the register (REG4) 39 as a reset signal (R3). The reset signal (R3) of the counter (counter 2) 38 is the output of the OR circuit (OR) 3B inverted by the inverter 37 ('rto;
)). The AND circuit (AND6) 40 connects the output (T4) of the timing set switch (SW) 2B and 11
．． Receives 6kHz (7) sample clock (CK),
The output (Tll; FIG. 2 (1)) becomes the input (IN) of the counter (counter 2) 38. The counter (counter 2) 38 counts the rising edge of the input (IN), and the count number of the counter (counter 2) 38 is registered in the register (RE).
G4) 39 inputs. Register (REG4) 39
stores the value of the counter (counter 2) 38 at the rising edge of the output of the OR circuit (OR) 3f3. Register (RE
When the output of the AND circuit (AND3) 33 is +1, the G4) 39 holds the stored data until a training start command is received. AND circuit (A
The ND8) 41 compares the data in the register (REG4) 39 and the value in the counter (counter 2) 38, and outputs a value of +1 if the two are equal. This output signal enters one input of an AND circuit (AND7) 42. The other input of the AND circuit (AND7) 42 is connected to the AND circuit (A
The output signal of ND3) 33 is input. AND circuit (AND7
) 42 enters one input of an AND circuit (AND9) 43. The other input of the AND circuit (AND9) 43 receives a 9.8kHz sample clock (CK
) is input, and the output signal (T9) of the AND circuit (AND9) 43 is output by the OR circuit (OR) 3B to the reset signal (R
5). The data stored in the register (REG4) held by the AND circuit (AND3) 33 is
This is the timing cycle data at the end of training.

FIG. 3 is a flowchart showing the operation when performing control using digital signal processing technology. The calculations in this flowchart are performed every l samples. In step 101, the BPF output is input through the input terminal 21 and stored in the register (REGI) 22. Step 102
Then, it is determined whether or not to start the training game. If it is determined that the training is to be started, the process proceeds to step 103, where the number of training symbols is set, and the timing set switch (SW) 2B, counter (counter l) 30, and The counter (counter 2) 38 is reset and the process proceeds to step 104. Further, if it is determined in step 102 that training has not started, the process proceeds to step 104. In step 104, it is determined whether the training has been completed, and if the training has not been completed, step 1
Proceed to 05. In step 105, the determination circuit detects the zero cross point of the rising edge of the timing input. If there is no zero cross point, the process advances to step 106. In step 106, it is determined whether the timing controller 1 switch (SW) is on or off, and it is turned off.
If so, proceed to step 11B, where the register (RE
Transfer the value of Gl) 22 to register (REG2) 23. On the other hand, when the zero cross point of the rising edge of the timing input is confirmed in step 105, the process proceeds to step 107, where the level of the timing input is determined. When the timing input exceeds a certain value, the process proceeds to step 108, where the timing set switch (SW) 28 is turned on, and the process proceeds to step 109. If the timing input does not exceed a certain value, the process proceeds to step 108. In step 108, the timing set switch (SW) 28 is turned on and off.
ff is checked and if it is determined to be on, step 11
0, the value of the counter (counter 2) 38 is stored in the register (RE).
G4) Store in 38. Next, in step 2 111, the counter (counter 2) 38 is reset, and then in step 112, 1 is added to the counter (counter 2) 38. Also, l is added to the counter (counter 1) 30.

Thereafter, in step 11B, the value of the register (REGI) 22 is transferred to the register (REG2) 23. Also, proceed to step 6 step 116 and perform the same processing. On the other hand, step 1
When completion of training is confirmed in step 04, the process proceeds to step 113, where it is determined whether the value of the register (REG4) 38 and the value of the counter (counter 2) 38 are equal. If the two values are equal, step 114
The counter (counter 2) 38 is reset.

Thereafter, in step 115, 1 is added to the counter (counter 2) 38, and the process proceeds to step 116. Also step 11
If the two values are not equal in step 3, and if it is confirmed that the timing set switch (SW) 28 is on in step lOθ, the process proceeds to step 115, in which 1 is added to the counter (counter 2) 38, and the process proceeds to step 116, as described above. It performs predetermined processing such as, and then moves on to another program.

The timing reproduction output uses the value of the counter (counter 2) 38 as the timing output, and the fixed phase delay for importing the symbol data into the automatic vase is the counter (counter 2).
It can be set by selecting 38 values.

FIG. 4 is a chart showing a flow (step 120) that can be added to the flow of FIG. 3 to reset the timing even during training.

This flow includes steps 104 and 113 in Figure 3.
added between steps 120-1 and 120
- Consists of 3. By adding this flow, if a timing reproduction output larger than a certain value is obtained even when not training, that timing signal can be prioritized over the previous timing signal, making it possible to obtain more accurate timing. Become. Note that this part of the flow can be added to the digital circuit.

(Effects of the Invention) As explained in detail above, according to the present invention, timing is regenerated during the training period and the timing period is fixed at the end of the training, so there is no need to use a scrambler circuit on the transmitting side. When transmitting data using mobile communication such as a car phone, there is an advantage that even if an error occurs, there is no increase in data errors due to the scrambler. Furthermore, since the unstable component of the timing signal due to the removal of the scrambler is eliminated, it is possible to create a data modem device with fewer data bit errors.

[Brief explanation of the drawing]

Fig. 1 is a main circuit diagram of an embodiment in which the timing regeneration circuit of the present invention is realized by a digital circuit, Fig. 2 is a time chart of the main part of Fig. 1, and Fig. 3 is a diagram showing when control is performed using digital signal processing technology. Operation flowchart, 4th
The figure is a flowchart showing a flow that can be added to the flow in Figure 3 to reset the timing even when not training. Figure 5 is a block diagram of a timing extraction circuit in a conventional timing regeneration circuit. Figure 6 is a block diagram of a timing extraction circuit in a conventional timing regeneration circuit. FIG. 2 is a timing APC circuit block diagram in a timing regeneration circuit. 21-m-input terminal 22.23, 32.39-m-register 24.25, 2
? -m-judgment circuit 2B, 29, 31, 33, 35, 40, 41, 42.4
3---AND circuit 28-11 timing set switch 30.38---one power switch 34.37---inverter 311f---OR circuit 44-m-timing output terminal 45-m-clock input terminal

Claims (2)

[Claims] (1) A first means for receiving a timing signal extracted from a received signal, adjusting the initial phase of the timing signal using a training signal, and determining whether to start training; and receiving an output of the first means for training. a second means for counting the number of symbols; and a third means for determining the end of training based on the output of the second means.
means, a fourth means for receiving training completion information from the third means and storing timing cycle data at the time of training completion, and generating a timing reproduction output based on the output from the first means. and a fifth means for outputting a timing reproduction output of a fixed timing period by comparison with the fourth means after the training is completed. (2) a first means for receiving a timing signal extracted from a received signal, adjusting the initial phase of the timing signal using a training signal and determining whether to start training; and receiving an output of the first means during training. a second means for counting the number of symbols; a third means for determining the end of training based on the output of the second means; A fourth means for storing periodic data and a timing reproduction output are generated based on the output from the first means, and after the training is completed, the fixed timing period is determined by comparing the contents with the fourth means. For data transmission, comprising a fifth means for outputting a timing reproduction output, and a sixth means for resetting the fifth means when a timing reproduction output of a certain value or more is obtained. Modem timing recovery circuit.