JPS58161549A - Timing extracting circuit - Google Patents

Abstract

PURPOSE:To realize the optimum timing extraction even in case an echo component is included, by setting the fixed threshold value and the variable threshold value which is larger than the fixed threshold value and controlling the variable threshold value to set the pulse width of the slice output at a fixed level. CONSTITUTION:A bipolar input signal is converted into a signal of positive or negative polarity by a full-wave rectifying circuit 2 and applied to slicing circuits 3 and 4. The circuit 4 performs slicing with the first fixed threshold value; while the circuit 3 uses the second threshold value controlled by a control circuit 6 to perform the slicing. The circuit 6 decides an echo signal with a deciding output of a polarity deciding circuit 5 if a primary signal and its following signal have the same polarity. The circuit 6 controls the second threshold value when it is decided a signal is not equal to an echo signal and so that the slice output of the circuit 3 is set at the prescribed pulse width within a period during which the slice output of the circuit 4 exists. Then the slice output is delivered through a terminal 7 as a signal which is used for extraction of timing.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a timing extraction circuit for extracting a timing signal for identifying an input signal on the receiving side of a digital signal transmission system.

Prior Art and Problems Digital signal transmission systems require a timing signal to identify signals whose waveforms have been distorted due to transmission lines, etc., and the timing signal is usually extracted from the input signal. . As a means for extracting this timing signal, zero-crossing point detection or slicing using a certain threshold is known. However, since the zero-crossing point changes depending on the signal pattern, zero-crossing point detection has the disadvantage that the extracted timing signal has large jitter. In addition, timing extraction by slicing may cause the center of the slice output signal to shift from the peak point position of the input signal when an echo component is included in the input signal, or the slice output may cause the echo component to be considered as one of the input signals. There were cases where a signal could be obtained, and there was a drawback that an accurate timing signal could not be extracted.

OBJECT OF THE INVENTION The present invention provides a method for detecting an input signal that includes an echo component.
The purpose of this is to enable extraction of a desired timing signal with small jitter.

Examples will be described in detail below.

Embodiment of the Invention FIG. 1 is an explanatory diagram of the principle of the present invention. In timing extraction by the slice method, the threshold value is set near the half value of the amplitude of the input signal. By slicing the input signal containing the echo component shown in FIG. 2 using the threshold value TRI, the slice output shown in FIG. If the center position B of this slice output deviates from the peak point of the input signal, it will not be possible to reproduce the timing signal at the optimal discrimination point of the input signal.

Therefore, it is conceivable to set a threshold value TH2 larger than the threshold value THI, slice the input signal near the peak point, and obtain the slice output shown in FIG. 1(e). In this case, the center position C almost coincides with the peak point A of the input signal, and the timing signal at the optimal discrimination point can be reproduced K.
Become. However, since the amplitude of the input signal varies depending on various conditions such as the transmission path, timing extraction cannot be performed in the case of an input signal with an amplitude lower than the threshold value TH2.

Further, as shown in FIG. 1(d), when the delay of the echo component is large and the amplitude is also relatively large, the threshold value is set to THl,
No matter which setting TH2 is set, a slice output of the main signal and the echo signal E cannot be obtained, but accurate timing extraction cannot be performed.

Therefore, the present invention sets a first threshold THI that can detect an input signal within the amplitude fluctuation range of the input signal, and a second threshold TH2 that is larger than the first threshold THI.
is controlled so that the pulse width T of the slice output shown in FIG. 1(e) remains constant. As a result, the center position C of the slice output based on the threshold [1TH2 always almost coincides with the peak point A of the input signal, and by applying this slice output to a tank circuit or the like, the timing signal is regenerated.

Furthermore, if the input signal is a bipolar signal as shown in Figure 1(d), for example, when an AMI code is used, a positive polarity signal is always followed by a negative polarity signal, so that the positive polarity main signal is Since the next positive echo signal E can be identified,
The slice output of the echo signal E is removed so that it is not used to create a timing signal.

FIG. 2 is a block diagram of an embodiment of the present invention, in which a bipolar signal as shown in FIG. 1(d) is input. In Figure 2, 1 is an input terminal,
2 is a full-wave rectifier circuit, 3 is a second slice circuit, and 4 is a first
5 is a polarity determination circuit, 6 is a control circuit for controlling the second threshold value and slice output, and 7 is an output terminal.

A bipolar input signal is converted into a signal of either positive or negative polarity by a full-wave rectifier circuit 2 and is applied to slice circuits 3 and 4.

The first slicing circuit 4 slices at a fixed first threshold TI (1), and the second slicing circuit 3 slices at a second threshold TH2 controlled by the control circuit 6. For example, when the polarity of the input signal is positive, “l”
When # is negative, it is judged as “02”, and as shown in Figure 1 (d
), if the next signal after the main signal has the same polarity,
The control circuit 6 determines that the echo signal E is based on the succession of 'bi' and 'bi'.

When the control circuit 6 determines that it is not the echo signal E,
The second threshold value is controlled so that the pulse width T of the slice output of the second slice circuit 3 becomes a predetermined constant size within the period in which the slice output of the first slice circuit 4 exists. Then, this slice output is output from the output terminal 7 as a signal for timing extraction, and is applied to, for example, a tank circuit.

FIG. 3 is a block diagram of the control circuit 6 according to the embodiment of the present invention, where 9 and INI are input terminals for the determination signal from the polarity determination circuit 5, and IN2 is an input terminal for the slice output from the first slice circuit 4. terminal, INS is a high-speed clock input terminal, I
N4 is the input terminal of the slice output from the second slice circuit 3, 0UTI is the output terminal of the signal for timing extraction, 0UT2 is the output terminal of the second M([, FF1 to FF
4 is a flip-flop, CTRI, CTR2 is a counter, CMP is a comparator, DAC is a DA converter, G
l, G2 is an exclusive OR circuit, 03 to G6 are AND circuits,
G7. G8 is a NAND circuit, G9 is an OR circuit, Gl(1,
Gll is an inverter. Also, CK is a clock terminal, D
are data terminals, Q, Q are output terminals, CE is a count enable terminal, CL is a clear terminal, U/D is a terminal for instructing up-counting or down-counting, al is the count content X of counter CTRL is predetermined. Range x1~
Comparison output terminal G2 that outputs '1# when x2 is within x1, that is, x1≦X≦x2, and outputs 10# otherwise.
outputs l" when X2 ()c and counter CTR2
This is an output terminal that instructs the counter CTR2 to count up, and otherwise outputs "0" to instruct the counter CTR2 to count down.

When the slice output of the first slice circuit 4 applied to the input terminal IN2 becomes IP', the flip-flop FF3
is set first, and then flip-flop FF4 is set one clock cycle later. flip flop FF
When only 3 is set, the clock from the input terminal IN3 is sent to the flip-flop FFI via the NAND circuit G7.
, FF2, and the polarity determination signal from the polarity determination circuit 5 is applied to the input terminal INIK. Flip-flop FFI just before that,
Assuming that both FF2 are in the reset state, when the polarity determination signal is "1", the output of the exclusive OR circuit Gl becomes 'IN', and the flip-flop FFI is set at the clock timing. The output of OR circuit G1 is 0", and the output of exclusive OR circuit G2 is "1".
” becomes.

Next, when the slice output from the second slice circuit 3 is applied to the input terminal IN4, it is output to the output terminal OUT 1 via the AND circuit G6, and the counter CTRI
Since the counter CTRI is added as a count enable signal to the clock, the counter CTRI counts the clock. Therefore, the counter CTRI counts the clock during the slice output period of the second slice circuit 3, and when the slice output of the first slice circuit 4 becomes 10'' and the flip-flop FF3 is reset, the NAND Circuit G8
The output of CTRI becomes '0' at the clock timing, and the counter CTRI is cleared.

Also, the count content x of the counter CTRI is the comparator C
When x1≦X≦x2, the comparison output terminal a1 is “1#” and the output of the AND circuit G5 is 0.
Since it remains #, the counter CTR2 does not count the clock, and the count contents of the counter CTR2 are added to the DA converter DAC and the analog I! 20 threshold is applied to the second slice circuit 3 from the output terminal OUT 2.

In the case of x1), the comparison output terminal a1 becomes "o", the output terminal a2 becomes "0#", and when the flip 70 tube FF3 is reset, the output of the AND circuit G4 becomes "51", and the output of the inverter Gll becomes "51". @11n1 exclusive OR circuit G2
Since the output of the AND circuit G5 is '1', the count enable signal of the output of the AND circuit G5 becomes '11', and the output of the terminal U/
Since "0" is added to D, the counter CTR2 is counted down. The level of the second threshold value of the output of the DA converter DAC is thereby reduced. That is, if the pulse width of the slice output of the second slice circuit 3 is smaller than the predetermined value, then! The threshold value of IfJ2 becomes smaller.

In addition, if X2<X, the comparison output terminal altl"0", G
2 becomes 11", the counter CTR2 counts up the clock, and the second threshold value of the output of the DA converter DAC increases. With this operation, the second threshold value is controlled, and the second threshold value is The pulse width of the slice output from the second slice circuit 3 is controlled to be constant.

In addition, when the polarity determination signal is continuously "L", flip-flops FF1 and FF2 are both set, so the output of exclusive OR circuits Gl and G2 becomes P0#, and AND circuit G6
is closed, the slice output of the second slice circuit 3 does not appear at the output terminal OUT1, and the count contents of the counter CTR2 remain unchanged. The same holds true when the polarity determination signal is continuously "0". That is, only when the polarity determination signal alternately repeats "l#, m□IT", the second threshold value is controlled and the slice output of the second slice circuit 3 is output to the output terminal 0UTI.

Figure WJ4 is a block diagram of the main parts of an embodiment that controls the threshold value of tJ12 by analog processing.
is turned on by the slice output of the second slice circuit 3, and the operational amplifier 10. Capacitor CI.

A constant voltage V is applied to an integrating circuit consisting of a resistor R1.

Therefore, the integral output is as shown in FIG. 5(a).
Since it corresponds to the pulse width of the slice output in b), the comparator 11 compares it with the reference voltage vr and outputs the second threshold value. This second threshold value is controlled so that the level becomes large when the pulse width is large, and becomes small when the pulse width is small, so that the pulse width of the slice output is controlled to be constant. In addition, 82 in FIG. 4 is a switch element, which is a switch element for initial setting to set the output of the integrating circuit to zero.

As described in detail, the present invention is capable of slicing only the vicinity of the peak of an input signal to generate a signal for timing extraction, so even if an echo component is included, optimal timing extraction can be achieved. becomes possible. Furthermore, in the case of a bipolar input signal such as an AMI code, even if the echo component has a large delay, the echo component can be removed and the signal can be used for timing extraction. Note that the configuration for controlling the second threshold value is l! Digital processing shown in Figure 3 and 1
The present invention is not limited to the analog processing configuration shown in FIG. 4, and various configurations may be adopted as long as the pulse width of the output signal of the second slice circuit 3 can be controlled to be constant. It's something you get.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of a control circuit of an embodiment of the invention, and Fig. 4 is an implementation of the invention. FIG. 5 is a block diagram of the main part controlling the second threshold value by the analog processing of the example, and is an explanatory diagram of the operation of FIG. 4. 1 is an input terminal, 2 is a full-wave rectifier circuit, 3 is a second slice circuit, 4 is a first slice circuit, 5 is a polarity determination circuit, 6
is a control circuit, and 7 is an output terminal. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Hisa Gobe Tamamushi (3 others) Figure 1

Claims (2)

[Claims] (1) In a timing extraction circuit that extracts a timing signal from an input signal, a first slicing circuit that slices the input signal at a fixed first threshold; a second slicing circuit that slices with a threshold of 2 and outputs a signal for timing extraction; the pulse width of the output signal of the second slicing circuit within the period of the output signal of the first slicing circuit; A timing extraction circuit comprising: a control circuit that controls the level of the second threshold value so that the level of the second threshold value is constant. (2) A timing extraction circuit that extracts a timing signal from a bipolar input signal includes a rectifier circuit that full-wave rectifies the bipolar input signal, and a first circuit that slices the output signal of the rectifier circuit at a fixed first threshold value. a slicing circuit; a second slicing circuit that slices the output signal of the rectifier circuit using a second threshold value that is larger than the first threshold value and outputs a signal for timing extraction; a second slicing circuit that determines the polarity of the bipolar input signal; a polarity determination circuit, the second slice circuit so that the pulse width of the output signal of the WJ2 slice circuit within the period of the output signal of the first slice circuit is constant;
and when the polarity determination circuit determines that the polarity of the bipolar input signal is in a predetermined order, outputs the output signal of the second slice circuit as a signal for timing extraction. 1. A timing extraction circuit comprising: a control circuit for controlling the timing extraction circuit;