JPH0119669B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a timing extraction circuit for extracting a timing signal for identifying an input signal on the receiving side of a digital signal transmission system.

Prior Art and Problems In a digital signal transmission system, a timing signal is required to identify a signal whose waveform is distorted due to a transmission path, etc., and the timing signal is usually extracted from an input signal. As means for extracting this timing signal, zero-crossing point detection or slicing using a certain threshold is known. However, since the zero-crossing point changes depending on the signal pattern, zero-crossing point detection has the disadvantage that the extracted timing signal has large jitter. In addition, timing extraction by slicing may cause the center of the slice output signal to shift from the peak point position of the input signal when an echo component is included in the input signal, or the slice output may cause the echo component to be considered as one of the input signals. There were cases where a signal could be obtained, and there was a drawback that an accurate timing signal could not be extracted.

OBJECTS OF THE INVENTION It is an object of the present invention to make it possible to extract a desired timing signal with small jitter even from an input signal containing an echo component.
Examples will be described in detail below.

Embodiment of the Invention FIG. 1 is an explanatory diagram of the principle of the present invention. In timing extraction by the slice method, the threshold value is set near the half value of the amplitude of the input signal, so the method shown in FIG. The input signal including the echo component is sliced at the threshold value TH1, and the slice output shown in FIG. 2B is obtained. The center position B of this slice output is shifted from the peak point A of the input signal, making it impossible to reproduce the timing signal at the optimal discrimination point of the input signal.

Therefore, we set a threshold TH2 that is larger than the threshold TH1, slice the area near the peak point of the input signal, and
It is possible to obtain the slice output shown in Figure c. In this case, the center position C almost coincides with the peak point A of the input signal, and the timing signal at the optimal discrimination point can be reproduced. but,
Since the amplitude of the input signal varies depending on various conditions such as the transmission path, timing extraction cannot be performed if the input signal has an amplitude lower than the threshold value TH2.

Furthermore, as shown in Figure 1d, if the delay of the echo component is large and the amplitude is relatively large, the main signal D
A slice output of the echo signal E and the echo signal E will be obtained, and accurate timing extraction will not be possible.

Therefore, the present invention provides a first threshold value TH1 that allows the input signal to be detected within the amplitude fluctuation range of the input signal.
and a second threshold value TH2 larger than the threshold value TH2, and control the second threshold value TH2 so that the pulse width T of the slice output shown in FIG. 1c becomes constant. As a result, the center position C of the slice output based on the threshold value TH2 always almost coincides with the peak point A of the input signal, and by applying this slice output to a tank circuit or the like, the timing signal is regenerated.

Furthermore, when the input signal shown in Figure 1d is a bipolar signal, for example when an AMI code is used, the next signal after a positive polarity signal is always a negative polarity signal, so that the next signal after a positive polarity main signal D Since the positive polarity echo signal E can be identified, the slice output of the echo signal E is removed so that it is not used to create a timing signal.

FIG. 2 is a block diagram of an embodiment of the present invention, in which a bipolar signal as shown in FIG. 1d is input. In Figure 2, 1 is the input terminal, 2 is the full-wave rectifier circuit, and 3 is the second
4 is a first slice circuit, 5 is a polarity determination circuit, 6 is a control circuit for controlling the second threshold value and the slice output, and 7 is an output terminal. A bipolar input signal is converted into a signal of either positive or negative polarity by a full-wave rectifier circuit 2 and is applied to slice circuits 3 and 4.

The first slice circuit 4 has a fixed first threshold value.
The second slicing circuit 3 sets a second threshold TH2 controlled by the control circuit 6.
Slice. In addition, the polarity determination circuit 5 outputs "1" when the polarity of the input signal is positive, and "0" when the polarity of the input signal is negative.
As shown in FIG. 1d, if the next signal of the main signal D has the same polarity, the control circuit 6
is determined to be an echo signal E based on a series of "1" and "1".

When the control circuit 6 determines that the echo signal is not the echo signal E, the pulse width T of the slice output of the second slice circuit 3 is set to a predetermined value within the period in which the slice output of the first slice circuit 4 exists. The second threshold value is controlled to have a constant magnitude, and this slice output is output from the output terminal 7 as a signal for timing extraction, and is applied to, for example, a tank circuit.

FIG. 3 is a block diagram of the control circuit 6 according to the embodiment of the present invention, where IN1 is an input terminal for the determination signal from the polarity determination circuit 5, IN2 is an input terminal for the slice output from the first slice circuit 4, IN3 is a high-speed clock input terminal, IN4 is an input terminal for slice output from the second slice circuit 3, and OUT1 is an input terminal for the slice output from the second slice circuit 3.
is the signal output terminal for timing extraction,
OUT2 is the second threshold output terminal, FF1 to FF4
is a flip-flop, CTR1 and CTR2 are counters, CMP is a comparator, DAC is a DA converter,
G1 and G2 are exclusive OR circuits, G3 to G6 are AND circuits, G7 and G8 are NAND circuits, G9 is an OR circuit, and G10 and G11 are inverters. Also CK
is a clock terminal, D is a data terminal, Q is an output terminal, CE is a count enable terminal, C is a clear terminal, U/D is a terminal that indicates whether to count up or down, a1 is the counter CTR1.
a comparison output terminal that outputs "1" when the count content x is within a predetermined range _x1 to _x2 , that is, _x1 ≦x≦ _x2 , and outputs "0"otherwise;
2 outputs “1” when x ₂ < x and runs the counter
This is an output terminal that instructs CTR2 to count up, and otherwise outputs "0" to instruct counter CTR2 to count down.

When the slice output of the first slice circuit 4 applied to the input terminal IN2 becomes "1", the flip-flop FF3 is set first, and then the flip-flop FF4 is set one clock cycle later. When only flip-flop FF3 is set, input terminal IN3 is input via NAND circuit G7.
The clock from is flip-flop FF1, FF2
The polarity determination signal from the polarity determination circuit 5 is applied to the input terminal IN1. Flip-flop FF1 just before that,
Assuming that both FF2 are in the reset state, when the polarity determination signal is "1", the exclusive OR circuit G
1 becomes "1", and flip-flop FF1 is set at the clock timing. As a result, the output of exclusive OR circuit G1 is "0",
The output of exclusive OR circuit G2 becomes "1".

Next, when the slice output from the second slice circuit 3 is applied to the input terminal IN4, the AND circuit G
6 to the output terminal OUT1, and
Since it is applied to the counter CTR1 as a count enable signal, the counter CTR1 performs clock counting. Therefore, the counter CTR1 counts the clock during the slice output period of the second slice circuit 3, and when the slice output of the first slice circuit 4 becomes "0" and the flip-flop FF3 is reset, the NAND clock is counted. The output of circuit G8 becomes “0” at the clock timing.
Therefore, the counter CTR1 is cleared.

Further, the count content x of the counter CTR1 is added to the comparator CMP, and when x ₁ ≦x≦x ₂ , the comparison output terminal a1 is “1” and the AND circuit G
Since the output of 5 remains “0”, the counter
CTR2 does not count the clock, but the count contents of counter CTR2 are added to the DA converter DAC, and the analog second threshold is output to the output terminal.
It is applied to the second slice circuit 3 from OUT2.

In addition, when x ₁ > x, the comparison output terminal a1 is “0”,
The output terminal a2 becomes “0” and the flip-flop
When FF3 is reset, the output of AND circuit G4 is "1", the output of inverter G11 is "1",
Since the output of the exclusive OR circuit G2 is "1", the count enable signal output from the AND circuit G5 becomes "1", and "0" is added to the terminal U/D, so the counter CTR2 starts counting down. be done. Thereby, the level of the second threshold value of the output of the DA converter DAC is reduced. That is, when the pulse width of the slice output of the second slice circuit 3 is smaller than a predetermined value, the second threshold value becomes smaller.

In addition, when x ₂ <x, the comparison output terminal a1 is “0”,
a2 becomes “1”, counter CTR2 counts up the clock, and the DA converter
The second threshold of the output of the DAC is increased. The second threshold value is controlled by such an operation, and the pulse width of the slice output of the second slice circuit 3 is controlled to be constant.

Furthermore, when the polarity determination signal is continuously "1", flip-flops FF1 and FF2 are both set, so the outputs of exclusive OR circuits G1 and G2 become "0", AND circuit G6 is closed, and the output terminal
The slice output of the second slice circuit 3 does not appear on OUT1, and the counter CTR
The count contents of 2 remain unchanged. The same holds true when the polarity determination signal is continuously "0". That is, only when the polarity determination signal alternately repeats "1" and "0", the second threshold value is controlled and the slice output of the second slice circuit 3 is outputted to the output terminal OUT1.

FIG. 4 is a block diagram of essential parts of an embodiment in which the second threshold value is controlled by analog processing, in which the switch element S1 is turned on by the slice output of the second slice circuit 3, the operational amplifier 10, the capacitor C1, the resistor A constant voltage V is applied to the integrating circuit consisting of R1. Therefore, as shown in FIG. 5a, the integrated output corresponds to the pulse width of the slice output in FIG.
A second threshold value is output in comparison with V _r . This second
The threshold value is controlled so that the level becomes large when the pulse width is large, and becomes small when the pulse width is small, so that the pulse width of the slice output is controlled to be constant. Furthermore, the fourth
S2 in the figure is a switch element, which is used for initial setting to set the output of the integrating circuit to zero.

Effects of the Invention As explained above, the present invention is controlled by the first slicing circuit 4 which slices the input signal at a fixed first threshold TH1, and the control circuit 6, and which is larger than the first threshold TH1. a second slicing circuit 3 for slicing at a second threshold TH2;
The second threshold value TH2 is set by the control circuit 6 so that the pulse width of the output signal of the slice circuit 3 is constant.
Since it is possible to slice only the vicinity of the peak value of the input signal and use it as a signal for timing extraction, it is possible to extract the optimal timing even if the input signal contains echo components. This has the advantage of being possible.

In the case of a bipolar input signal such as an AMI code, full-wave rectification is performed by the full-wave rectifier circuit 2, and only the vicinity of the peak value of the input signal is sliced by the above-mentioned processing, and the signal is sliced according to the polarity order of the bipolar input signal. The output signal of the second slice circuit 3 is selected and used as a signal for timing extraction.
Even when the echo component in a bipolar input signal such as an AMI code has a large delay, this echo component can be removed, so there is an advantage that optimal timing extraction is possible.

Note that the configuration for controlling the second threshold value TH2 is not limited to the configuration using the digital processing shown in FIG. 3 and the analog processing shown in FIG. Various configurations can be adopted as long as the pulse width can be controlled to be constant.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of a control circuit of an embodiment of the invention, and Fig. 4 is an implementation of the invention. FIG. 5 is a block diagram of the main part of controlling the second threshold value by the analog processing of the example, and is an explanatory diagram of the operation of FIG. 4. 1 is an input terminal, 2 is a full-wave rectifier circuit, 3 is a second slice circuit, 4 is a first slice circuit, 5 is a polarity determination circuit, 6 is a control circuit, and 7 is an output terminal.

Claims (1)

[Claims] 1. In a timing extraction circuit that extracts a timing signal from an input signal, a first slicing circuit that slices the input signal using a fixed first threshold;
a second slicing circuit that slices the input signal using a second threshold value that is larger than the first threshold value and outputs a signal for timing extraction; A timing extraction circuit comprising: a control circuit that controls the level of the second threshold so that the pulse width of the output signal of the second slice circuit is constant. 2. In a timing extraction circuit that extracts a timing signal from a bipolar input signal, a rectifier circuit that full-wave rectifies the bipolar input signal, and a first slice circuit that slices the output signal of the rectifier circuit at a fixed first threshold value. , a second slicing circuit that slices the output signal of the rectifier circuit using a second threshold value that is larger than the first threshold value and outputs a signal for timing extraction; and a polarity determination circuit that determines the polarity of the bipolar input signal. , controlling the level of the second threshold so that the pulse width of the output signal of the second slice circuit within the period of the output signal of the first slice circuit is constant; and the polarity determination circuit. and a control circuit that outputs the output signal of the second slice circuit as a signal for timing extraction when it is determined that the polarity of the bipolar input signal is in a predetermined order. extraction circuit.