JPH02179115A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To eliminate noise when the pulse time width of a signal and noise is close to each other by applying logical processing to the pulse time width of a component of a sensor signal. CONSTITUTION:Flip-flops 1-3 operated synchronously with a clock pulse signal CLK corresponding to the pulse time width of a sensor signal Si are provided to detect a pulse whose width is shorter than the pulse time width of the sensor signal is detected. Then a pulse shorter than the noise time width of the detection signal is detected. Then the sensor signal including the noise pulse is applied to gate circuits 5-7 and a flip-flop 8 to eliminate the noise pulse. Thus, even when the pulse time of the signal component and noise component is close to each other, the noise pulse is sufficiently eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing circuit for receiving a digital signal output from an optical sensor or the like and removing noise from the signal that changes over time.

2. Description of the Related Art Conventionally, this type of digital signal processing circuit includes a filter circuit for the purpose of removing noise contained in the signal when processing the digital signal output from the sensor.

FIG. 3 shows an example of a conventionally used filter circuit, which is a so-called low-pass filter whose purpose is to remove noise having a duration shorter than the pulse time width of a sensor signal.

In the example in Figure 3, C is made up of a capacitor and a resistor.
This circuit attempts to discriminate between amplitude differences and remove small amplitude noise pulses by reducing the amplitude of noise pulses shorter than the pulse time width of the resensor signal due to the effect of the R time constant.

The conventional circuit shown in FIG. 3 is also effective when the difference in time width between the sensor signal and the noise pulse is large enough to be distinguishable as a difference in amplitude.

Problems to be Solved by the Invention However, since the conventional example described above includes a time constant circuit, there is a problem that when the difference in time width between the sensor signal and the noise pulse becomes small, it becomes impossible to discriminate the sensor signal and the noise pulse.

For example, if the pulse train of the sensor signal 25 in FIG.
If the shaded portion is a noise pulse as shown in s, the signal 26 that has passed through the CR time constant circuit is 1 in FIG.
If the voltage VTH of the battery 23, which gives the threshold value T of the comparator 24 when it becomes 1, is 1 in 11 in FIG. 4, the signal of the comparator output 27 becomes as shown in ta in FIG.
The noise pulse shown in the hatched area will remain. When the time width of the noise pulse changes, there is a problem that noise cannot be removed unless the threshold voltage or CR time constant is changed.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent digital signal processing circuit that can remove noise when the pulse time widths of a signal and noise are close to each other.

Means for Solving the Problems In order to achieve the above object, the present invention provides a flip-flop that operates in synchronization with a clock pulse signal corresponding to the pulse time width of the sensor signal, and generates a pulse shorter than the pulse time width of the sensor signal. is detected, and the detected signal is applied to a sensor signal containing noise pulses using a gate circuit and a flip-flop to remove the noise pulses.

Effects The present invention has the following effects due to the above structure. That is, a clock pulse signal equal to the minimum pulse time width of the sensor signal is used as a synchronization signal for each flip-flop, and the sensor signal is input to the D input of the first D flip-flop to determine the rise or fall of the synchronization signal. Sampling is performed on either one. The output of the first flip-flop is connected to the D input of a second D flip-flop, and the second flip-flop is sampled with a synchronization signal that is in opposite phase to the first 7-resop-flop. On the other hand, the sensor signal is connected to the D input of the third D flip-flop and sampled with a synchronization signal that is in phase with the second flip-flop.

Each output of the second and third 7-lip-frogs is connected to an input of an exclusive OR gate circuit. Therefore, in the pulse train of the sensor signal, there is a noise pulse such that the logical value of the senna signal at the time when the first flip-flop is sampled is different from the logical value of the senna signal at the time when the third flip-flop is sampled. In this case, the logic value "1" is detected in the output of the exclusive OR gate circuit, and the output of the exclusive OR gate circuit is
When the above exclusive OR gate circuit output is a logical value rlJ at the J and K inputs of the flipflop, J and K are input.
If both inputs have a logical value of "0" and the output of the exclusive OR gate circuit has a logical value of "0", the Q output of the second flip-flop is input to the J input, and the Q output of the second flip-flop is input to the K input. It is connected to the fourth flip-flop through a gate circuit provided with an output. Since the fourth flip-flop is sampled with a synchronization signal that is in phase with the first flip-flop, the logic value of the output of the exclusive OR circuit is
0'', the output after sampling of the fourth flip-flop is the same as the first. Each sampling result of each second flip-flop is inherited, but if the logical value of the output of the exclusive OR circuit is "1", the output after sampling of the fourth flip-flop is the sampling output of the previous one. is maintained and at this point the noise pulse can be removed.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, Si indicates an input terminal for a sensor signal, CLK indicates a clock pulse signal, and SO indicates an output terminal for a sensor signal resulting from the operation of the present invention. 1 is CLK
D flip-flop, 2, which operates in synchronization with the rising edge of
and 3 are D flip-flops that operate in synchronization with the rising edge of a clock pulse signal made by inverting CLK with the inverter 4, 5 is a two-man exclusive OR gate with a negative logic output, and 6 and 7 are two-man power AND gates. , 8 are JK flip-flops that operate in synchronization with the rising edge of CLK, and are connected as shown in FIG.

Next, the operation of the above embodiment will be explained. Figure 2 is the first
3 is a timing chart showing the operation of the embodiment shown in the figure. T in Figure 2,, 'rt, Tmaro, T4゜T,,
Ts are 9.10.11.12.13 in Figure 1, respectively.
The timing of the point corresponding to ゜14 is shown.

The senna signal sampled at 1 in FIG. 11 at the timing shown at 15 in FIG. 2 is output from T in FIG. 2, and from Q at 2 in FIG.
The sensor signal sampled at the timing shown by 16 in the figure is output from Q of 3 in FIG. 1, and the both sides of the signal become the logical value shown by T@ in FIG. 2 by the exclusive OR gate of the negative logic output. The respective outputs of 6 and 7 in FIG. 1, which are two AND gates that act on the logic value and the Q output and Q output of 2 in FIG. 1 as inputs, are sent to the JK flip-flop 8 in FIG. The second sampled at the timing of 17
A logical value shown at T6 in the figure is obtained. 15 to 17 shown in Figure 2
The sensor signal of T1 shown at the timing of 17 to 20 is the case where there is no noise pulse, but the sensor signal of T1 shown at the timing of 17 to 20,
If there is a noise pulse as shown in the diagonally hatched area, the logical values of the sampling result at timing 18 and the result sampling at timing 19 do not match. In that case, the output of the exclusive OR gate changes like a T circuit at timing 19, and the logic value rOJ is input to both the J input and the input of the JK flip-flop sampled at timing 20. , the output after sampling remains unchanged and the noise pulses are removed.

In this way, according to the above embodiment, the sampling pulse time is set by focusing on the minimum time of the sensor signal pulse, and the pulse train of the sensor signal is sequentially sampled at the rising and falling edges of the sampling pulse, thereby changing the period of the sampling pulse. Sensor signals that change in a shorter period of time can be detected and removed as noise pulses.

Effects of the Invention As is clear from the above embodiments, the present invention performs logical processing focusing on the pulse time width of the signal component of the sensor signal, and unlike analog value processing using a time constant, the signal component and noise component are This has the advantage that noise pulses can be sufficiently removed even if the pulse time values of are close to each other.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a digital signal processing circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a filter circuit diagram showing an example of a conventional method, and FIG. The figure is a timing chart showing the operation of FIG. 3. 1, 2. 3... D flip-flop, 4... Inverter gate, 5... Exclusive OR gate with negative logic output, 6.7... 2-manual AND gate, 8... JK flip-flop, 9 ...Sensor signal, 1o...Clock pulse signal, 11...Output signal of flip-flop 2, 12...Output signal of flip-flop 3, 13
...output signal of gate 5, 14...output signal of flip 70 knob 8. Name of agent: Patent attorney Shige Awano Takaha 5! -Ichizu diagram J Diagram-11 → Yuchinkin question

Claims (1)

[Claims] A first D flip-flop samples an input signal with a timing pulse, and a second D flip-flop samples the output signal of the first flip-flop as an input signal with a timing pulse having a phase opposite to that of the first flip-flop.
a D flip-flop, a third D flip-flop that samples the input signal with a timing pulse in phase with the second flip-flop, an output of the third D flip-flop, and an output of the second flip-flop. The output is connected to the other input of two AND gates whose one input is respectively connected to the Q output and @Q@ output of the second flip-flop, and It was constructed with a JK flip-flop that takes the output of an AND gate that receives the positive output of a flip-flop as an input, and uses the output of the other AND gate as a K input and samples with a timing pulse in phase with the first flip-flop. Digital signal processing circuit.