SU1688412A1 - Delta-codec - Google Patents

Abstract

The invention relates to communication technology and computer technology and allows improving the codec immunity and ensuring that its characteristics are independent of the clock frequency. The delta codec consists of an encoder and a decoder. The encoder contains a low-pass filter 1, a comparator block 2, a discretionator 3 and an integrator 6. By introducing a divider 4 frequency into two, an analog adder 5, an integrator 7 and key elements 8-11, the instantaneous feedback circuit is removed and the integrators 6 are excluded. and 7 from the feedback circuit of the operational amplifier 30 of the adder 5. 1 Cp f-ly, 3 ill.

Description

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The invention relates to communication technology and computer technology and can be used in information transmission systems.

The purpose of the invention is to improve the noise immunity of the codec and to ensure that its characteristics are independent of the clock frequency.

Figures 1 and 2 depict functional diagrams of the encoder and the decoder, respectively; FIG. 3 shows the signals explaining the operation of the codec.

A codec consists of a coder and a decoder. The encoder contains (Fig. 1) lowpass filter 1, frequencies (LPF), comparison unit 2, sampler 3, divider 4 frequencies into two, analog adder 5, first 6 and second 7 integrators, first - fourth key elements 8-11 . In FIG. 1, information 12 and clock 13 inputs and output 14 of the encoder are indicated.

The decoder contains (figure 2) pulse shaper 15, frequency divider 16 by two, analog adder 17, first 18 and second 19 integrators, first to fourth key elements 20-23, and low pass filter 24, figure 2 indicates information 25 and clock 26 entrances and exits 27.

The encoder comparison unit 2 includes a subtractor 28 and a comparator 29.

The encoder 3 encoder and shaper 15 decoder pulses are D-flip-flops. The first and second outputs thereof are the forward and inverse outputs of the corresponding trigger.

Dividers 4 and 16 frequencies into two are made on counting triggers.

Analog adder 5 (17) is provided on an operational amplifier (OU) 30 and the first is a fifth resistor 31-35.

On fig.Z marked the following signals: a - clock pulses at the input 13 (26); b, c - signals on the direct and inverse outputs of the divider 4 (16) frequencies into two; (d) signals at the first C (t) and second X (t) inputs of comparator unit 2; d, e - voltage at the outputs of the first and second integrators 6 and 7, respectively; W - encoder output signal.

In the encoder, the analog adder 5, the integrators 6 and 7, and the key elements 8-11 form a local decoder-predictor.

The delta codec works as follows.

The input analog signal C (t) after filtering in the low-pass filter 1 is fed to the first

input of subtractor 28 in comparison unit 2, to the second input of which a signal X (t) of the local predictor decoder is applied. The subtractor 28 of block 2 forms a positive

output level, if C (t) X (t), and negative, if C (t) X (t), i.e.

U + C (t) - X (t) if C (t) X (t) (1)

U C (t) - X (t) if C (t) X (t). The comparator 29 in block 2 converts

the levels U and U in Log.1 when U +, or Log.O take place at U. These sequences of zeros or ones are written to the D-trigger of the sampler 3 at times determined by the fronts (e.g., positive) of clock pulses (TI). Thus, an isochronous random digital signal sequence is formed at the forward output of the sampler 3 D-flip-flop.

C ((g) -X (g) L Dt. (2)

where D t is equal to the period of the sequence of clock pulses TI.

The pulse sequence from the forward output of the D-trigger of sampler 3 is the output of the delta encoder. In addition, the straight line C (KDH) and inverse C (KDO sequences arrive at the corresponding inputs of the analog adder 5. The task of the local decoder-predictor COCTQHT is to form the most approximate copy X from the digital streams C (KD1) and C (KDt) t) the input signal C (t) as small as possible at each clock point from C (x). The control inputs of the key elements 8-11 receive pulses from the outputs of the 4 frequency divider by two so that, for example, in the nth clock interval closed key elements 9 and 10 and open elements 8 and 11, and in the next Blowing (n + 1) -th - elements 8 and 11 are closed, and 9 and 10. Thus, at each clock interval (for example, at the same n-th), the integrator voltage is 7

is the output of the local predictor decoder and constantly throughout the nth clock interval, and the charge of the integrator 6 is adjusted by the output current of the operational amplifier 30 of the adder

0 5 depending on the voltage of the integrator 7, which is currently the output, and the sign of the difference U or U (1), formed at the input of the comparator 29, and respectively, at the outputs of the D-trigger of the distributor 3. At the next cycle (for example, (n + 1) -m) key elements 8 and 11 are closed, and 9 and 10 are open, and the voltage of integrator 6 is the output signal of the local predictor decoder and is constant during the (n + 1) -th clock interval, and integrator charge 7 is adjusted, etc.

If a unit is written to the D-flip-flop of sampler 3, then a single symbol will also be on the first (direct) output of the sampler 3. This signal, via resistor 31, goes to the inverting input of operational amplifier 30 (the non-inverting input has a zero from the inverse output of the sampler 3), which leads to the appearance of a negative potential at the output of the amplifier 30 and its output current through the resistor 35 reduces the voltage of the integrator 6 or 7, the charge of which is corrected. If zero is written to the D-flip-flop of the sampler 3, then the unit potential goes through the resistor 32 to the direct input of the operational amplifier 30 (the potential is zero on the inverse), and therefore, the correction output current of the amplifier 30 is positive.

In other words, a negative feedback circuit tends to reduce the charge of integrators 6 and 7 during adjustment cycles, if C (t) X (t), and increase this charge, if C (t) X (t).

Thus, since in the next cycle in one of the integrators 6 or 7, with the adjustment through the closed key element 8 or 10, and in the other integrator 7 or 6, during the same cycle, the voltage is continuously and through the key element 11 or 9 the second input of unit 2 of the comparison, the instantaneous negative feedback circuit through the local decoder-predictor is open, which significantly increases the stability of the delta coder.

In addition, integrators 6 and 7 do not enter the feedback circuit of opamp 30, therefore, the drift currents of its differential inputs in integrators 6 and 7 do not accumulate. Resistors 33-35 serve to maintain the transfer coefficient of the adder 5 on the operational amplifier 30 equal to a constant predetermined value.

In the decoder (Fig. 2), the received digital stream of units / zeros C (CD1), after the preliminary restoration of temporary positions, enters the information input of the imaging unit 15 pulses, the clock input of which is supplied with clock pulses TI. The task of the decoder is to restore the most approximate form of the original analog signal C (t) by the received digital stream C (KDT).

Essentially, a decoder circuit replicates the structure and functions of a local decoder predictor coder. Formed copy X (t) of the input digital stream C (CD1) after filtering in the low-pass filter 24 goes to output 27.

Thus, since the instantaneous feedback circuit is open and the integrators b and 7 are not included in the feedback circuit of the OA 30, the noise immunity of the delta codec increases and does not depend on the clock frequency.

Claims (2)

Claim 1. A delta codec consisting of an encoder and a decoder, the encoder contains a low-pass filter whose input is the information input of the encoder, and the output is connected to the first input of the comparator, the output of which is connected to the information input of the sampler, the first output of which is the output of the encoder, and the first integrator, the decoder comprises a pulse shaper, whose information input is the information input of the decoder, the first integrator and a low-pass filter, the output of which is the decoder output, characterized in that, in order to improve the noise immunity of the codec and to ensure that its characteristics are independent of the clock frequency, an analog adder, a second integrator, the first to fourth key elements and a frequency divider for two, whose input in the encoder is combined with a clock input of the sampler, are entered into the encoder and decoder and is the encoder clock input, the first input of the analog adder in the encoder is connected to the first output of the sampler, the second output of which is connected to the second input of the analog adder, in the decoder clock The two frequency divider input is combined with the pulse driver clock input and is the decoder clock input. The first and second outputs of the decoder pulse generator are connected to the analog inputs of the analog adder, in the encoder and decoder, the direct and inverse outputs of the frequency divider are connected to two control outputs inputs of the second, third and first, fourth key elements, respectively, the output of the analog adder is connected to the information inputs of the first and third key elements, the outputs of which are respective first and second integrators connected respectively to the data inputs of the second and fourth key elements whose outputs are combined and connected in the encoder to the second input of the comparing unit and the third input of the analog adder, and a decoder - to the third the input of the analog adder and the input of the low pass filter. 2. The delta codec according to claim 1. that is, that the analog adder contains an operational amplifier and the first - fifth resistors, the first terminals of the first - the third resistors are respectively the first - the third inputs adder, second output first and first 0 the output of the fourth resistor is connected to the inverting input of the operational amplifier, the second terminals of the second and third resistors are connected to the non-inverting input of the operational amplifier, the output of which is connected to the first output of the fifth resistor, the second terminals of the fourth and fifth resistors are combined and are the output of the adder. njnjTJOJTjajiruT-njajTJTJ jnjTj-L Fig 2 / nl-k