JP2630091B2 - Alarm hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm holding circuit,
In particular, the present invention relates to an alarm holding circuit that performs alarm detection in a digital circuit.

[0002]

2. Description of the Related Art Conventionally, an alarm holding circuit holds an alarm by delaying alarm release using a monostable multivibrator, a resistor and a capacitor. At this time, the time to be delayed is defined by the time constant of the resistor and the capacitor.

[0003]

In the conventional alarm holding circuit, since the holding time is set by using a resistor and a capacitor, the holding time varies depending on the resistance value and the variation in capacitance. For this reason, the holding time is not constant, which may be unsuitable for processing in a digital circuit.

An object of the present invention is to provide an alarm holding circuit which eliminates such disadvantages and keeps the alarm holding time constant.

[0005]

An alarm holding circuit according to the present invention comprises a binary counter for inputting a clock to a clock input terminal and setting an initial value based on raw alarm information, and an alarm signal by inverting the output of the binary counter. And a gate circuit for sending a clock to the clock input terminal of the binary counter while the alarm signal from the inverting circuit is in the alarm state.

[0006]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The alarm holding circuit shown in FIG. 1 includes an AND gate 1, an n-bit binary counter 2, and an inverter gate 3.

In such an alarm holding circuit, the initial setting input of the n-bit binary counter 2 ("H" at the time of initial setting)
, A raw alarm b (“H” at the time of alarm) is input, and the output of the AND gate 1 is connected to the clock input of the n-bit binary counter 2. One of the two inputs of the AND gate 1 receives the clock a, and the other is connected to the output of the inverter gate 3. The input of the inverter gate 3 is the i output of the n-bit binary counter 2 (it becomes “H” when i is counted, and 0 ≦ i ≦ n).
Is connected. The output of the inverter gate 3 becomes the alarm output c.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

A clock a is applied to one input of the AND gate 1. A raw alarm b is added to the initial setting input of the n-bit binary counter 2.
When the raw alarm b changes from “L” to “H” (alarm state), n
The bit binary counter 2 enters an initial value setting state. At this time, the i output of the n-bit binary counter 2 is "L".
Becomes The signal from the i output is output from the inverter gate 3
And applied to the other input of AND gate 1. As a result, the AND gate 1 is opened,
Clock a passes through AND gate 1 and is applied to the clock input of n-bit binary counter 2.

Next, from the time when the raw alarm b changes from "H" to "L", the n-bit binary counter 2 starts counting up. When the binary counter 2 counts the set value i, the i output changes from "L" to "H", and the output of the inverter gate 3, that is, the alarm output c changes from "H" to "L" (alarm State). At the same time, since the clock a is inhibited by the AND gate 1, the output of the n-bit binary counter 2 is fixed at "H". As a result, this state is maintained until the raw alarm b becomes "H" (alarm state) next.

As described above, in this embodiment, an arbitrary clock is input to the clock input terminal, the output of the n-bit binary counter which is set to the initial value setting state by the raw alarm information is issued as an alarm, and the alarm is restored. Sometimes, the n-bit binary counter is stopped.

As a result, the present embodiment enables the holding time at the time of alarm release to be specified by i times the clock and obtains an alarm output synchronized with the clock, which is suitable for processing in a digital circuit.

[0014]

As described above, according to the present invention,
There is an effect that the holding time of the alarm becomes constant and is suitable for processing in a digital circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a time chart of the embodiment of FIG. 1;

[Explanation of symbols]

 1 n-bit binary counter 2 AND gate 3 inverter gate a clock b raw alarm c alarm output

Claims (1)

(57) [Claims] 1. A binary counter for inputting a clock to a clock input terminal and setting an initial value based on raw alarm information, an inverting circuit for inverting the output of the binary counter and sending an alarm signal, and an alarm signal from the inverting circuit. Is in the alarm state,
A gate circuit for sending a clock to a clock input terminal of a binary counter.