JPH10154922A - Comb-line filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively eliminate an excess offset included in a received digital signal by having only to add a small scale circuit to a conventional digital comb-line filter configuration. SOLUTION: The comb-line filter is provided with 1st filters 1-6 that receive a digital signal and have a transfer function (1-Z<-> K)N (K, N are natural numbers), 2nd filters 10-12 that consist of N-stages of series connection integration devices which receive outputs of the 1st filters 1-6, a detection means 16 that detects the polarity of the output of the 2nd filters 10-12 and increase/decrease means 17, 18 that generate an increase/decrease pulse to increase/decrease a value of the N-th stage integration device 12 in the 2nd filters 10-12 based on an output from the detection means 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comb filter used in the field of digital audio and the like, and more particularly to a comb filter having an offset removing function.

[0002]

2. Description of the Related Art Conventionally, as a comb filter of this type,
`` National Technical Report VOL.34No.2 Apr.1988 p.
p.43 "is known. The structure and operation of this comb filter will be described with reference to FIG.

The conventional comb filter 451 shown in FIG.
The data input via the data bus is transferred to the operation clock φ.
Three shift registers 401, 402, and 403 that delay by one 16 clocks, and a subtractor 41 that subtracts input data from the output of the last-stage shift register 403.
1, a subtractor 412 for subtracting the outputs of the middle-stage shift register 402 and the first-stage shift register 401, a multiplier 421 for tripling the output of the subtractor 412, and a subtractor 4
11 and an adder 413 for adding the output of the multiplier 421;
Three integrators 43 for sequentially integrating the output of the adder 413
1, 432, and 433.

[0004] Three shift registers 401, 402, 4
Since 03 Each of the transfer function is z ^-16, the transfer function of the output of the adder 413 as viewed from the ^{input, 1-3 · z -16 +3 · z} -32 -z -48 = (1-z - ¹⁶ ) It becomes ³ .

The total transfer function of the integrators 431, 432, and 433 is 1 / (1−z ⁻¹ ) ^3. Therefore, the overall transfer function of the comb filter 451 having this configuration is expressed by the following equation. As shown.

H (z) = (1-z ^-16 ) ³ / (1-z ^-1 ) ³ (1)

[0007]

The analog signal input to the A / D converter sometimes contains an extra offset. The analog signal including this offset is converted into an analog signal by the A / D converter. If the signal is input to the comb filter having the conventional configuration shown in FIG. 4 after the digitization, the offset filter cannot be effectively removed because the comb filter outputs a signal including the offset.

As a countermeasure, it is possible to remove the offset by connecting an offset removing device separately to the output side of the comb filter, but a dedicated offset removing device is provided separately for the comb filter. Then
The overall circuit scale becomes large.

The present invention has been made to solve the above problems, and it is an object of the present invention to effectively remove an input offset by adding a small-scale circuit to a conventional comb filter.

[0010]

According to the present invention, in order to solve the above-mentioned problems, a part of a comb filter can be shared as an offset removing circuit.
Specifically, the following configuration is adopted.

That is, according to the first aspect of the present invention, a digital signal is input, and a transfer function (1-z- ^K ) is obtained.
^A first filter having ^N (K and N are natural numbers), a second filter having an input of an output of the first filter, and an integrator connected in series across N stages, and a second filter output Detecting means for detecting the positive or negative of the signal, and increasing / decreasing means for generating an increasing / decreasing pulse for increasing / decreasing the value of the N-th integrator of the second filter based on the output from the detecting means.

According to this configuration, if the polarity of the output of the second filter is deviated to either direction, an increase / decrease pulse is generated, and the Nth
The control is performed in a direction in which the value of the integrator at the stage approaches “0”.

[0013] The second aspect of the present invention is the first aspect.
In the configuration described above, a decimation unit that performs decimation of the output of the second filter is provided, while the detection unit detects whether the output of the decimation unit is positive or negative.

According to this configuration, after the operation speed is reduced, when the polarity of the data is deviated to one of the polarities, an increase / decrease pulse is generated, and the value of the integrator at the Nth stage is set to "0". The control is performed in a direction approaching "."

According to a third aspect of the present invention, in the configuration according to the first or second aspect, the increasing / decreasing means integrates the output of the detecting means, and when the integrated value becomes a value equal to or more than a certain value. And outputting the increase / decrease pulse to the second filter and resetting the integrated value.

Also in this configuration, when the polarity of the output of the second filter becomes the same value for a certain period of time, an increase / decrease pulse is generated, and control is performed in a direction in which the value of the integrator at the Nth stage approaches "0". Done.

According to a fourth aspect of the present invention, in the configuration according to any one of the first to third aspects, the Nth
The integrator of the stage includes an adder and a register. The adder adds both outputs of the register and the integrator of the preceding stage, and adds ± 2 to the addition result according to an increase / decrease pulse from the increase / decrease means. The register stores the output of the adder and sends the output to the adder.

In this configuration, the integrator of the N-th stage causes the polarity of the output of the second filter to have the same value for a certain period of time, and each time the integrated value exceeds a certain value, the value is set to “0” one by one. The control is performed in the approaching direction.

According to a fifth aspect of the present invention, in the configuration according to the fourth aspect, the adder is provided with a carry input, and the increasing / decreasing means adds +1 to the adder. Adds 1 to the carry input,
When subtracting +1 from the adder, it is necessary to wait until the least significant bit of the input of the adder becomes "1", replace this value with "0", and input the value to the adder. In this configuration, when the value of the N-th integrator approaches “0” one by one, processing of input data to the adder is performed instead of using the subtractor even during subtraction. Can perform the subtraction.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a comb filter having an offset removing function according to Embodiment 1 of the present invention.

This comb filter is used, for example, for decimation of the output of a ΔΣ modulation type A / D converter for converting an analog signal into a digital signal by oversampling. It comprises shift registers 1, 2, 3 and subtracters 4, 5, 6.

Each of the shift registers 1, 2, 3 receives an operation clock φ1 from a digital signal input through a data bus.
The subtracters 4, 5, and 6 subtract the outputs of the shift registers 1, 2, and 3 from the input supplied to the + terminal, respectively. Then, these shift registers 1, 2, 3
And the subtracters 4, 5, and 6 correspond to a first filter in the claims.

Here, the transfer function of the output of the subtractor 6 at the final stage viewed from the input side is (1-z ^-16 ) ³ , which is shown in FIG.
This is the same as the output of the adder 413 of the conventional example shown by. In other words, the first filter constituted by the shift registers 1, 2, 3 and the subtracters 4, 5, 6 corresponds to the circuits 401, 402, 403, 411, 41 shown in FIG.
The same result can be obtained with the configuration of 2,421,413.

The integrators 10, 11, and 12 are similar to the integrators 431, 432, and 433 shown in FIG. 4 and each include an adder and a register. A second filter in the claims is configured. Therefore, each shift register 1, 2, 3,
And a first filter comprising subtractors 4, 5, and 6, and a second filter comprising series-connected integrators 431, 432, and 433.
The overall transfer function of the above filter is the same as that shown by the above-mentioned equation (1).

In the first embodiment, the last-stage integrator 12 is configured to integrate digital signals given from the preceding-stage integrator 11 and a threshold detector 18 described later. That is, this integrator 1
2 is that the adder 13 constituting this not only adds (or subtracts) the output of the register 14 and the output of the integrator 11 at the preceding stage but also the output from the threshold detector 18 described later. I have.

The decimation circuit 15 samples the input signal at a predetermined frequency, that is, performs decimation of data.

The positive / negative detector 16 is a decimation circuit 1
5, the polarity of the output is determined. More specifically, the MSB (most significant bit) of the data output from the decimation circuit 15 is monitored, and if the MSB is "1", -1 is set.
If B is "0", +1 is output.

The integrator 17 integrates the value output from the positive / negative detector 16 and a threshold detector 18
Normally outputs 0, but when the output of the integrator 17 exceeds a fixed positive value, +1 is set as an increase / decrease pulse, and when the output of the integrator 17 exceeds a fixed negative value, it is set as an increase / decrease pulse. -1 is output. When the threshold value detector 18 outputs such an increase / decrease pulse ± 1, the integrator 17 is reset.

Therefore, in the first embodiment, the integrator 17 and the threshold detector 18 correspond to an increasing / decreasing means in the claims.

Next, the operation of the comb filter shown in FIG. 1 will be described.

When the output from the threshold detector 18 is "0", the operation of the integrator 12 is exactly the same as the other integrators 10 and 11, and the output of the integrator 12 is as shown in FIG. Like the integrator 433 of the conventional example shown, it operates as an output of a normal comb filter.

Here, assuming that the digital signal input to the comb filter shown in FIG. 1 contains a positive offset, the frequency characteristics near DC in this comb filter are flat. Therefore, the frequency at which a positive value appears is higher than that at a negative value (that is, the frequency at which the MSB becomes “0” increases).

Therefore, the output of the positive / negative detector 16 outputs a value of +1 more than a value of -1.

Accordingly, the output of the integrator 17 gradually increases, and when the integrated value exceeds a predetermined value, this is detected by the threshold detector 18 and the increase / decrease pulse is output from the threshold detector plate 8. Is output as -1.
Since this increase / decrease pulse is given to the adder 13 of the integrator 12, the value of the integrator 12 is reduced by one. That is, the offset is reduced by one. By repeating this operation, the positive offset is gradually reduced.

The same applies to the case where the digital signal input to the comb filter of FIG. 1 includes a negative offset. At this time, the threshold detector 18 outputs +1 as an increase / decrease pulse. Then, the increase / decrease pulse is applied to the integrator 12
, The value of the integrator 12 increases by one. That is, the negative offset is reduced by one. By repeating this operation, the negative offset is gradually reduced.

When the integrator 12 is controlled using the data after decimation by the decimation circuit 15 as in the first embodiment, the operating speed of the integrator 17 and the threshold detector 18 is reduced. Since the operation is performed at a lower speed, power consumption can be reduced. Further, the word length of the integrator 17 can also be reduced in proportion to the decimation rate by the decimation circuit 15, and there is an advantage that the circuit scale can be reduced.

However, even if the output of the integrator 12 is directly input to the positive / negative detector 16 to detect the positive / negative without using the output of the decimation circuit 15 and the result is integrated by the integrator 17, the same applies. It goes without saying that an offset removing effect can be obtained.

Embodiment 2 FIG. 2 is a block diagram showing a main part of a comb filter according to Embodiment 2.

In the second embodiment, as shown in FIG. 2, an integrator 12 'is used instead of the integrator 12 in the subsequent stage shown in FIG.
Is composed of a register 14 and an adder 20, and an AND gate 21 and a control circuit 21 are further provided.
The integrator 17, the threshold detector 18, and the AND gate 21 and the control circuit 21 of FIG. 1 constitute an increasing / decreasing means in the claims.

The adder 20 has input terminals A and B for inputting the outputs of the register 14 and the integrator 11 at the preceding stage, and has a carry input terminal CI. In addition to the addition of the respective outputs of the eleventh output, when "1" (high-level pulse) is input to the carry input terminal CI, +1 is added, and the addition result is output from the output terminal S. I have.

The AND gate 22 is a signal obtained by inverting the level of the LSB (least significant bit) signal line of the digital signal input via the integrator 11 at the preceding stage and the output from the output terminal A of the control circuit 21. Are input together, and the logical product output of the two is applied to one input terminal B of the adder 20. In other words, only one LSB of the digital signal input through the integrator 11 at the preceding stage is set to AN.
The output is replaced by the output of the D gate 22.

The control circuit 21 has an input terminal C for an increase / decrease pulse from the threshold detector 18, an input terminal R for a signal line of an LSB (least significant bit) of a digital signal input via the integrator 11 at the preceding stage, and both ends. It has two output terminals A and B for outputting predetermined pulses according to the inputs of the children C and R, and is configured to perform the following operation.

When the increase / decrease pulse applied to one input terminal C from the threshold detector 18 is "0", both output terminals A and B output "0" regardless of the input of the other input terminal R.

The increase / decrease pulse applied to one input terminal C is +
In the case of 1, "0" is output from one output terminal A and "1" is output from the other output terminal B regardless of the input of the other input terminal R.

The increase / decrease pulse applied to one input terminal C is-
In the case of 1, the other output terminal B always outputs "0" irrespective of the input of the other input terminal R. As for one output terminal A, the input of the other input terminal R is “0”.
In this case, "1" is always output. When the input of the other input terminal R becomes "1", "1" is delayed by one clock φ.
The level is inverted from "0" to "0".

The other structure is the same as that of the first embodiment shown in FIG.
Therefore, detailed description is omitted.

Next, the operation of the configuration shown in FIG. 2 will be described.

First, when the output of the threshold detector 18 is "0", the control circuit 21 outputs "0" from both the output terminals A and B. The data applied to the adder 12 ′ is directly provided to the adder 20. At this time, carry input terminal C of adder 20
Since the input of I is also "0", a normal integration operation is performed.

Next, since the digital signal passing through the comb filter includes a negative offset,
Outputs +1, the control circuit 21 outputs "0" from one output terminal A and "1" from the other output terminal B. In response to this, the gate of the AND gate 22 is opened, so that the input of the LSB (least significant bit) of the digital signal input to the integrator 12 ′ passes through the input without change and is input to the adder 20. . Since “1” is given to the carry input terminal CI of the adder 20, the adder 20 further adds +1 to a value obtained by adding the outputs of the register 14 and the integrator 11 at the preceding stage, and outputs the result. That is, since the integrator 12 'outputs a value obtained by adding +1 extra than the normal operation, the above operation is repeated even if the output of the integrator 12' includes a negative offset. By doing so, the negative offset is gradually removed.

On the other hand, since the digital signal passing through the comb filter includes a positive offset,
Outputs -1, the control circuit 21 outputs "1" from one output terminal A and "0" from the other output terminal B.

In response, the gate of AND gate 22 is closed and its output becomes "0".
LSB (least significant bit) of digital signal input to 2 '
When the input is "0", it is simply replaced with the same value, so that the normal integration operation is performed. In this state, when the LSB of the digital signal input to the integrator 12 'becomes "1", the control circuit 21 does not immediately change the output of the one output terminal A to "0" and delays by one clock φ. And then “0”
Level is inverted.

Therefore, the AND gate 22 is connected to the integrator 1
Even when the LSB of the digital signal input to 2 ′ becomes “1”, the gate remains closed for one clock φ, so that the digital signal input to this integrator 12 ′ (The least significant bit) is replaced from “1” to “0”. This is equivalent to the LSB of this digital signal being reduced by -1. Also,
At this time, the output of the other output terminal B of the control circuit 21 is always "0", which is applied to the carry input terminal CI of the adder 20, so that the adder 20 does not perform the operation of +1.

Therefore, every time -1 is given as an increase / decrease pulse from the threshold detector 18 to the control circuit 21, a value obtained by extra subtracting -1 from the integrator 12 'is output from the integrator 12'. Therefore, even if a positive offset is included in the output of the integrator 12 ', the positive offset is gradually removed by repeating the above operation.

With the configuration shown in FIG. 2, both the positive and negative offsets can be effectively removed only by the adder 20 without providing a subtractor, so that the circuit scale is greatly reduced. Becomes possible.

Third Embodiment FIG. 3 is a block diagram showing a main part of a comb filter according to a third embodiment.

In the third embodiment, the integrator 12 ″ is composed of the register 14 and the two adders 20 and 30, and the increasing / decreasing means is composed of the two AND gates 21 and 32 and the control circuit 21. doing. That is, the adder 30 and the AND gate 32 are further added to the configuration shown in FIG.

Here, even if the offset contained in the input digital signal is less than the LSB, the digital signal input to the integrator 12 '' is set to 14 so that the offset can be effectively removed. When the number of bits is three, three bits are further added for offset removal.

That is, the AND gate 30 can obtain the same three-bit data as a logical product output with respect to the LSB signal line of the digital signal from the integrator 11 at the preceding stage. Further, the adder 30 is provided in the register 1
4 together with the lower 3 bits of the 17 bits of the data outputted from 4 and the output of 3 bits of the AND gate 32, and when a high-level pulse is inputted to the carry input terminal CI, +1 is added. The addition result is output from an output terminal S. When the addition value of both input terminals A and B exceeds the range of numbers handled by the adder 30, the carry output terminal CO outputs "1". "
(High-level pulse).

Other structures are the same as those of the respective structures shown in FIGS. 1 and 2, and a detailed description thereof will be omitted.

Next, the operation of the configuration shown in FIG. 3 will be described.

First, when the output of the threshold detector 18 is "0", the control circuit 21 outputs "0" from both output terminals A and B.
Is output to the integrator 12 and the data signal is directly supplied to the adder 20. At this time, AND
The gate 32 is closed and its output is "0".
Therefore, "0" is input to the input terminal B of the adder 30 and "0" is also added to the carry input terminal CI of the adder 30.
, The lower 3 bits of the 17 bits of the data provided from the above are output as they are, and a normal integration operation is performed.

Next, since the digital signal passing through the comb filter includes a negative offset,
Outputs +1, the control circuit 21 outputs "0" from one output terminal A and "1" from the other output terminal B. In response to this, the gate of one AND gate 22 is opened, and the LSB of the digital signal input to the integrator 12 ″ passes through the gate as it is. Also, the gate of the other AND gate 32 is closed and its output is "0", so that "0" is input to the input terminal B of the adder 30, but the carry input terminal CI of the adder 30 is Is supplied with “1”, the adder 30 outputs the lower 3 bits of the 17 bits of the data supplied from the register 14.
+1 is further added to the bit data and output. Then, since the output of the adder 30 is added to the register 14, when the integrator 12 ″ is viewed as a whole, 1/2 ³ =
1/8 is added, and a value which is +1/8 as compared with the normal integration operation is output.

As described above, if the integrator 12 '' includes a negative offset, the above operation is repeatedly performed, and the offset is gradually removed.

Next, since the digital signal passing through the comb filter contains a positive offset,
Outputs -1, the control circuit 21 outputs "1" from one output terminal A and "0" from the other output terminal B.

In response, the gate of one AND gate 22 is closed and the gate of the other AND gate 32 is opened. At this time, the LSB of the digital signal input to the integrator 12 '' is When the input of (the least significant bit) is "0", the outputs of both AND gates 22 and 32 are both "0". In this case, a normal integration operation is performed.

In this state, when the LSB of the digital signal input to the integrator 12 ″ becomes “1”, the control circuit 2
1 does not immediately change the output of one output terminal A to “0”, but inverts the level to “0” after a delay of one clock φ.

Therefore, the AND gate 22 is connected to the integrator 1
Even when the LSB of the digital signal input to 2 ″ becomes “1”, the gate remains closed for a period of one clock φ, so that the signal is input to this integrator 12 ″. (Least significant bit) of the digital signal is changed from “1” to “0”. Also, the AND gate 32
Even when the LSB of the digital signal input to the integrator 12 ″ becomes “1”, the gate remains open for a period of one clock φ, and thus the AND gate 3
The outputs of the three bits 2 are both “1”, and this is added by the adder 30 to the lower 3 bits of the 17-bit data output from the register 14. At this time,
The output of the other output terminal B of the control circuit 21 is always "0", which is applied to the carry input terminal CI of the adder 30, so that the adder 30 does not perform +1 operation.

Therefore, "011" is added to the lower 4 bits of the register 14 instead of adding "1000".
1 "is added. That is, 1/8 is reduced as compared with the normal integration operation.

As described above, every time -1 is given as an increase / decrease pulse from the threshold value detector 18 to the control circuit 21, the integrator 12 '' subtracts an extra -1/8 of the normal integration operation. Since the set value is output, even if a positive offset is included in the output of the integrator 12 ″, the positive offset is gradually removed by repeating the above operation.

With the configuration shown in FIG. 2, even when the amount of the offset to be removed is equal to or less than the LSB of the signal input to the integrator 12 ″, no special subtractor is provided.
Since both the positive and negative offsets can be effectively removed only by the adder 20, the circuit scale can be significantly reduced.

In each of the first to third embodiments, the shift registers 1, 2, 3 and the integrators 10, 11, 12 are used.
Are connected in series with each other, but the present invention is not limited to such three, and those having N (natural number) shift registers and integrators are included in the present invention. .

[0072]

According to the present invention, since a part of the comb filter can be shared as a circuit for removing the offset, the offset of the output of the comb filter can be effectively removed only by adding a small-scale circuit. can do.

In particular, in the structure of claim 5, N
Especially, the integrator at the stage can effectively remove both the positive and negative offsets only by the adder without providing a subtractor, so that the circuit scale can be largely reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a comb filter according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a main part of a comb filter according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram showing a main part of a comb filter according to Embodiment 3 of the present invention.

FIG. 4 is a block diagram showing a conventional comb filter.

[Explanation of symbols]

 1-3 shift registers 4-6 subtractors 10-12, 17 integrators 13, 20, 30 adders 14 registers 15 decimation circuits 16 positive / negative detectors 18 threshold detectors 21 control circuits

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideaki Hatanaka 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (5)

[Claims] A digital signal is input to a transfer function (1).
−z ^−K ) ^N (K and N are natural numbers), a second filter including an integrator that receives an output of the first filter as an input and is connected in series over N stages; Detecting means for detecting whether the output of the second filter is positive or negative; increasing / decreasing means for generating an increasing / decreasing pulse for increasing / decreasing a value of an integrator at the Nth stage of the second filter based on an output from the detecting means; A comb-shaped filter comprising: 2. The comb filter according to claim 1, further comprising: decimation means for decimation of the output of the second filter, wherein the detection means detects whether the output of the decimation means is positive or negative. Characteristic comb filter. 3. The comb filter according to claim 1, wherein said increasing / decreasing means integrates an output of said detecting means, and when the integrated value becomes a value equal to or more than a predetermined value, said second increasing / decreasing means outputs said second value. A comb filter configured to output an increase / decrease pulse to the filter and to reset the integrated value. 4. The comb filter according to claim 1, wherein the N-th stage integrator includes an adder and a register,
The adder adds both the output of the register and the output of the integrator at the preceding stage, and adds or subtracts ± 1 to or from the addition result in accordance with the increase / decrease pulse from the increase / decrease means. A comb filter storing an output and transmitting the output to an adder. 5. The comb filter according to claim 4, wherein said adder has a carry input, and said increasing / decreasing means applies said carry input to said adder when adding +1 to said adder. When adding 1 to the adder and subtracting +1 from the adder, wait until the least significant bit of the adder input becomes "1", and then set this value to "0".
Characterized in that the filter is configured to be input to the adder.