GB2278247A  Chopperstabilized sigmadelta converter  Google Patents
Chopperstabilized sigmadelta converter Download PDFInfo
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 GB2278247A GB2278247A GB9310144A GB9310144A GB2278247A GB 2278247 A GB2278247 A GB 2278247A GB 9310144 A GB9310144 A GB 9310144A GB 9310144 A GB9310144 A GB 9310144A GB 2278247 A GB2278247 A GB 2278247A
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Classifications

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03F—AMPLIFIERS
 H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
 H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
 H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M3/00—Conversion of analogue values to or from differential modulation
 H03M3/30—Deltasigma modulation
 H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
 H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
 H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
 H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
 H03M3/34—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching by chopping

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03F—AMPLIFIERS
 H03F2200/00—Indexing scheme relating to amplifiers
 H03F2200/331—Sigma delta modulation being used in an amplifying circuit

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M3/00—Conversion of analogue values to or from differential modulation
 H03M3/30—Deltasigma modulation
 H03M3/39—Structural details of deltasigma modulators, e.g. incremental deltasigma modulators
 H03M3/412—Structural details of deltasigma modulators, e.g. incremental deltasigma modulators characterised by the number of quantisers and their type and resolution
 H03M3/422—Structural details of deltasigma modulators, e.g. incremental deltasigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
 H03M3/43—Structural details of deltasigma modulators, e.g. incremental deltasigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M3/00—Conversion of analogue values to or from differential modulation
 H03M3/30—Deltasigma modulation
 H03M3/458—Analogue/digital converters using deltasigma modulation as an intermediate step
Abstract
Description
2278247 TITLE CHOPPERSTABILIZED SIGNADELTA ANALOGTODIGITAL CONVERTER
is
BACKGROUND OF THE INVENTION
The present invention relates generally to a analogtodigital converters(ADC), and more particularly to a chopperstabilized sigmadelta ADC using a chopper stabilizer to remove the circuit lowfrequency noises, so that the resolution of the sigmadelta ADC is greatly increased.
At present, the interface circuits of the sigmadelta ADC have been widely used in the VLSI(Very LargeScale Integration) application products. For example, in case of the telecommunication products, they can be applied to the integrated service digital network (ISDN) U interface, 9600 MODEM(Modem V.32 9600 bps), pulse code modulation codedecoder (PCM CODEC), etc. In comsumer electronic products, they can be applied to digital audio tape (DAT) recorders, compact disc (CD) player systems, and so on. In instrumentation products, they can be applied to 5 1/2 digital panel meters which can resolve a 1 MV signal. In these system, only the digital processing (DSP) chip connected behind the sigmadelta ADC needs to be differently designed to meet the requirements for different products. Therefore, it can be seen that the sigmadelta ADC is generally applied to various IC (Integrated Circuit) application products.
1 Referring to Figs. 14 and 15, conventional sigmadelta ADCs are typically constituted by a switchedcapacitor circuit. Such a technology can refer to S. R. Norsworth, 11Oversampled SigmaDelta Data Converter", ISCAS190 Workshop, New Orleans, LA, April 30, 1990. The sigmadelta ADC is a discretetime system, and its relationship between input and output signals can be described in zdomain wherein z=ejw, and w is an angular frequency. The relationship between w and the continuous signal frequency f can be characterized by w=2rf/f,, wherein fs is the sampling frequency of system.
The sampling frequency fs= 1/T, wherein T is the sampling period. If the continuous signal frequency f= fs/2, the angular frequency w = v. In this specification, the description for the sigmadelta ADC are all in zdomain.
Referring to Figs. 1(a) to 1(e), there is shown a conventional sigmadelta ADC 10, and its transfer function can be characterized in zdomain by Y(z)=X(z)ST(z)+ Q(z)NT(z), z=ejw wherein ST(z) is signal transfer function, and NT(z) is a noise transfer function. As shown in Fig. 1(b), the signal transfer function ST(z) is characterized by having a passband in the lowfrequency range to permit the input low frequency signal passing through. As shown in Fig. 1(c), the noise transfer function NT(z) is characterized by having a very high attenuation in the lowfrequency range to attenuate a large part of the lowfrequency qucntization noise which is generated when the input signal passes 2 through the analogtodigital converter A/D (this A/D is a lowbit analog todigital converter, and usually outputs only one bit) of the sigma delta ADC 10. In this way, the quantization noise will not be too large in the lowfrequency portion to interfere the passing of the normal signal. As shown in Figs. 1(d) and 1(e), the quantization noise generated when the input signal x passes through the sigmadelta ADC 10 is very small in lowfrequency portion. However, since the signal transfer function ST(z) has a passband in the lowfrequency range, the other circuit lowfrequency noises (except the quantization noise), for example the 1/f noise and the offset voltage of the operational amplifier, will also pass through the sigmadelta ADC 10 at the same time as the normal lowfrequency signal, so that the output digital signal y will be contaminated. Therefore, circuit lowfrequency will limit the sigmadelta ADC 10 to reach higher resolution, for example 2! 16 bits.
Known methods of reducing the lowfrequency in a sigma delta ADC circuit are usually derived from method of reducing the lowfrequency noise in conventional switched capacitor circuits, for example use of a chopperstabilized operational amplifier to replace the operational amplifier(may refer to U.S. Patent No. 4,939,516) or the correlated double sampling technology. Since these methods all solve this lowfrequency noise problem from the circuit angle, they can only overcome part of the problem.
3 Typical examples of the prior sigmadelta ADC are shown in Figs. 14 to 17. Fig. 14 shows a prior 1order sigmadelta ADC structure, and Fig. 15 shows a circuit designed on the basis of the structure shown in Fig. 14. Fig. 16 shows a prior singleinputtosingleoutput 2order onebit sigmadelta ADC structure, and Fig. 17 shows a circuit designed on the basis of the structure shown in Fig. 16. the blocks of Z'/(lZ1) can be e implemented by the circuit as shown in Fig. 5(b). Since the structures and circuits shown in Figs. 5(b), 14, to 17 are all clear to those skilled in the art, it is deemed unnecessary to describe them further. other prior sigmadelta ADCs are constituted by similar manner, as shown in U.S. Patent Nos. 5,068,660; 4,983,975; 4,972,436; 4,972,360; 4,939,516; and 4,920,544.
SUMMY OF THE INVENTION The primary object of the present invention is to provide a chopper stabilized sigmadelta analogtodigital converter(ADC) to solve the abovementioned lowfrequency noise problem and thus to greatly increase the resolution of the sigma delta ADC. The present invention approaches this problem from the system angle and technology, quite different from the circuit angle in the prior arts.
Another object of the present invention is to provide a chopperstabilized sigmadelta ADC which has a simple circuit complexity, is easy to design and can be manufactured without any special processing technologies.
4 1 In accordance with the present invention, a chopperstabilized sigmadelta analogtodigital converter comprises: a first discretetime multiplier adapted to receive an analog input signal and a first discretetime sequence, and capable of multiplying the analog input signal by the first discretetime sequence to produce a choppered analog signal; and a chopper sigmadelta analogto digital converter (ADC) connected in series to the first discretetime multiplier in order to receive an convert the choppered analog signal into a digital output signal, the chopper sigmadelta ADC being characterized in zdomain by:
is Y1(z)=Xl(z)ST1(z)+ Q(z)NT1(z), z=ejw wherein ST1(z) is a signal transfer functionj and is characterized by having a passband in a highfrequency range; and NV(z) is a noise transfer function, and characterized by having a high attenuation in the highfrequency range.
In accordance with another aspect of the present invention, a chopperstabilized sigmadelta ADC further comprises a second discretetime multiplier connected in series to the chopper sigmadelta ADC in order to receive the digital output signal, the second discretetime multiplier adapted to receive a second discretetime sequence, and multiplying the digital output signal by the second discretetime sequence to produce a choppered digital signal.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be more fully understood by reference to the following description and accompanying drawings, which form an integral part of this application:
Figs. 1(a) to 1(e) illustrate the structure and characteristics of a conventional sigmadelta analogtodigital converter (ADC); Figs 2(a) to 2(h) illustrate the structure and characteristics of a chopperstabilized sigmadelta ADC according to a first preferred embodiment of the present invention, which is suitable for a fully differential circuit implementation; Figs. 3(a) to 3(h) illustrate the structure and characteristics of a chopperstabilized sigmadelta ADC according to a second preferred embodiment of the present invention, which is suitable for a singleinput toto singleoutput circuit implementation; Figs. 4 shows the control clocks indicated in all circuit diagrams of the drawings; Figs. 5(a) and 5(b) illustrate the z domain symbols and circuit diagrams of two conventional singleinputtosingleoutput building blocks; Fig. 5(c) illustrate the zdomain symbol and circuit diagram of a singleinputtosingleoutput building block according to the present invention; 6 Fig. 6(a) illustrate the zdomain symbol and circuit diagram of a conventional fullydifferential building block; Fig. 6(b) illustrate the zdomain symbol and circuit diagram of a fully differential building block according to the present invention; Fig. 7(a) illustrate the zdomain symbol and circuit diagram of a conventional gain building block; Fig. 7(b) illustrate the zdomain symbol and circuit diagram of a gain building block according to the present invention; Fig. 8 is a structural block diagram of a 1order chopperstabilized sigmadelta ADC with Z'/(l+Zl) as building block, designed on the basis of the structure as shown in Fig. 2; Fig. 9 is a schematically elect rical diagram of a fullydifferential 1 order onebit chopperstabilized sigmadelta ADC with Z1/(l+Z1) as building block, designed on the basis of the structure of Fig. 8; Fig. 10 is a structural block diagram of a 1order chopperstabilized sigmadelta ADC with ZI/(I+Zl) as building block, designed on the basis of the structure as shown in Fig. 3; Fig. 11 is a schematically electrical diagram of a singleinputtosingle output 1order onebit chopperstabilized sigmadelta ADC with Z'/(l+Z1) as building block, designed on the basis of the structure of Fig. 10; 7 Fig. 12 is a structural block diagram of a 2order chopperstabilized sigmadelta ADC with Z1/(I+Zl) as building block, designed on the basis of the structure as shown in Fig. 2; Fig. 13 is a schematically electrical diagram of a fullydifferential 2 order onebit chopperstabilized sigmadelta ADC with Z1/(l+Zl) as building block, designed on the basis of the structure of Fig. 12; Fig. 14 is a structural block diagram of a conventional 1order sigmadelta ADC; Fig. 15 is a schematically electrical diagram of a conventional Iorder sigmadelta ADC circuit designed on the basis of the structure of Fig. 14, wherein an equivalent is noise source is added; Fig. 16 is a structural block diagram of a conventional 2order sigma delta ADC; Fig. 17 is a schematically electrical diagram of a conventional 2order sigmadelta ADC circuit designed on the basis of the structure of Fig. 16, wherein two equivalent noise sources are added; Fig. 18 is similar to Fig. 9, but an equivalent noise source is added further; Fig. 19 is similar to Fig. 13, but two equivalent noise source are added further; Figs. 20(a) and 20(b) show the simulation spectrums of the circuits as shown in Figs. 15 and 18; and 8 Figs. 21(a) and 21(b) show the simulation spectrums of the circuits as shown in Figs. 17 and 19.
Figs. 21(a) and 21(b) show the simulation spectrums of the circuits as shown in Figs. 17 and 19.
9 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In this description, two kinds of chopperstabilized sigmadelta analogtodigital converters (ADCs) of the present invention are disclosed. Fig. 2(a) shows the first kind of chopperstabilized sigmadelta ADC structure bk9 which is suitable for a fullydifferential circuit implementation. Fig. 3(a) shows the second kind of chopperstabilized sigmadelta ADC structure bk18 which is suitable for a singleinputtosingleoutput circuit implementation.
Referring now to Fig. 2(a), the chopperstabilized sigmadelta ADC structure bk9 according to the first preferred embodiment of the present invention includes a discretetime multiplier bkI, a chopper sigmadelta ADC bk3, and another discretetime multiplier bk4, connected together in series. The discretetime multiplier bki receives an input analog lowfrequency signal x, and a discretetime sequence bk2 consisting of alternating 11111 and 11111 digital signals, and multiplies them to produce a signal xt. The chopper sigmadelta ADC bk3 especially designed by the present invention receives and converts the output signal xl of the discretetime multiplier bki into a digital signal output yf. The discretetime multiplier bk4 receives the output signal y' of the chopper sigmadelta ADC bk3, and a discretetime sequence bk5 consisted of alternating 11111 and "111 digital signals, and multiplies them to produce a digital output signal y for the entire chopperstabilized sigmadelta ADC bk9.
Referring to Figs. 2(a) to 2(h), Figs. 2(b) to 2(d) illustrate the characteristics of the chopper sigmadelta ADC bk3, and Figs. 2(e) to 2(h) are diagrams of the halfspectrums of respective signals at different points in the chopperstabilized sigma delta ADC bk9. The multiplication operation conducted by the discrete time multiplier bkl is called a "chopper" multiplication, and can modulate the input lowfrequency signal x having a center frequency at wx, as shown in Fig. 2(e), into a signal having a center frequency at (r + wx) which, in the halfspectrum, is represented by a signal xI having a center frequency at (v wx), as shown in Fig. 2(f). The transfer function of the chopper sigmadelta ADC bk3 can be characterized in the z domzin by:
Yl(z)=Xf(z)STI(z) + Q(z)NTI(z), z=ejw wherein STI(z) is the signal transfer function, and NTI(z) is the noise transfer function. As shown in Fig. 2(c), the signal transfer function STI(z) is characterized by having a passband in the highfrequency range, i.e. the area around the angular frequency r, to permit the input highfrequency signal, i.e. the signal around the angular frequency r, to pass through. As shown in Fig. 2(d), the noise transfer function NTI(z) is characterized by having a very high attenuation in the highfrequency range to attenuate a large part of the quantization noise in highfrequency which is 11 is generated when the input signal passes through the analogtodigital converter A/D(this A/D is a lowbit analogtodigital converter, and usually outputs only one bit) of the chopper sigmadelta ADC bk3. In this way, the quantization noise will not be too large in highfrequency portions to interfere with the passing of the normal highfrequency signal. Fig. 2(g) shows the spectrum of the output digital signal yl, and the circuit lowfrequency noise joins in at this time. The "chopper" multiplication of the discretetime multiplier bk4 choppers the output signal yl of the chopper sigmadelta ADC bk3 to produce the finally desired digital signal y. The spectrum of the digital signal y is shown in Fig. 2 (h). In this way, there is only a small quantization noise in the lowfrequency range, and the circuit lowfrequency noise is choppered to the highfrequency range by the "chopper" multiplication of the discretetime multiplier bk4, so as not to affect the resolution. Since both of the input and output signals of the discretetime multiplier bk4 are all in digital forms, the discretetime multiplier bk4 may be designed in the digital signal processing(DSP) chip connected behind the sigmadelta ADC. That is to say, the chopperstabilized sigmadelta ADC bk9 of the present invention may omit the discretetime multiplier bk4.
Referring now to Fig. 3(a), the chopperstabilized sigmadelta ADC structure bk18 according to the second preferred embodiment of the present invention includes a 12 discretetime multiplier bklO, a chopper sigmadelta ADc bk12, and another discretetime multiplier bk13, connected together in series. The discretetime multiplier bkio receives an input analog lowfrequency signal x, and a discretetime sequence bkil consisting of alternating 11111 and 'toy', and multiplies them to produce a signal xl. The chopper sigmadelta ADC bk12 also especially designed by the present invention receives and converts the output signal xl of the discretetime multiplier bk10 into a digital signal output Y1. The discretetime multiplier bk13 receives the output signal y' of the chopper sigmadelta ADC bk12, and a discretetime sequence bk14 consisting of alternating 11111 It111, and multiplies them to produce a digital output signal y for the entire chopperstabilized sigmadelta ADC bk18.
Ref erring to Figs. 3 (a) to 3 (h), Figs. 3 (b) to 3 (d) illustrate the characteristics of the chopper sigmadelta ADC bk12, and Figs. 3(e) to 3(h) are schematic diagrams of the halfspectrums of respec tive signals at different points in the chopperstabilized sigmadelta ADc bk18. The "chopper" multiplication conducted by the discretetime multiplier bkio which receives the discretetime sequence bk11 obtains a little different result from the Uchopper" multiplication conducted by the discretetime multiplier bkl which receives the discretetime sequence bk2 as shown in Fig. 2(a). The discretetime multiplier bkio modulates only half of the input lowfrequency signal x having a center frequency at wx, as shown Fig. 3(e), into a signal having a 13 center frequency at (v + wx) which, in the halfspectrum, is represented by a signal having a center frequency at (vwx), while the other half of the input signal x still stays in the lowfrequency range, as shown in Fig. 3(f). The transfer function of the chopper sigmadelta ADC bk12 can be characterized in the z domzin:
Y1(z)=X1(z)ST1(z)+ Q(z)NTI(z), z=ejw wherein STI(z) is the signal transfer function, and NTI(z) is the noise transfer function. As shown in Fig. 3(c), the signal transfer function STI(z) is characterized by having a passband in the highfrequency range to permit the input highfrequency signal passing through. As shown in Fig. 3(d), the noise transfer function NTI(z) is characterized by having a very high attenuation in the high frequency range to attenuate a large part of the quantization noise in highfrequency which is generated when the input signal passes through the analogtodigital converter A/D (this A/D is a lowbit analogtodigital converter, and usually outputs only one bit) of the chopper sigmadelta ADC bk12. In this way, the quantization noise will not be too large in highfrequency portion to interfere the passing of the normal highfrequency signal. Fig. 3(g) shows the spectrum of the output digital signal yl, and the circuit lowfrequency noise joins in at this time. The "chopper" multiplication of the discretetime multiplier bk13 choppers the output signal yl of the chopper sigmadelta ADC bk12 to produce the final output digital signal y. The spectrum of the digital 14 signal y is shown in Fig. 3(h). In this way, the circuit lowfrequency noise is choppered to the highfrequency range by the "chopper" multiplication of the discretetime multiplier bk13, so as not to affect the resolution. In addition, there will be a 0.5time linear error in this embodiment because only half of the input lowfrequency signal x is modulated to the highfrequency range, i.e. the input lowfrequency signal x is half attenuated before entering the analogtodigital converting process. However, this linear error can be compensated in the digital signal processing chip later. Since both of the input and output signals of the discretetime multiplier bk13 are all in digi tal form, the discretetime multiplier bk13 may be designed in the digital signal processing (DSP) chip is connected behind the sigmadelta ADC. That is to say, the chopper stabilized sigmadelta ADC bk18 of the present invention my omit the discretetime multiplier bk13.
In sum, the function of the chopperstabilized sigma delta ADC structure bkg in accordance' with the first embodiment of the present invention can be characterized in zdomain by:
Y(z)=X(z)ST(z) + Q(z)NT(z), z=ejw That is to say, it achieves the same transfer function as the conventional sigmadelta ADC. The function of the chopperstabilized sigmadelta ADC structure bk18 in accordance with the second embodiment of the present invention can be characterized in zdomain by:
Y(z)=0.5X(z) ST(z) + Q(z)NT(z), z=ejw It also achieves the same transfer function as the conventional sigma delta ADC, except a 0.5time linear error. As mentioned above, this linear error can be compensated in the DSP chip. Therefore, the chopperstabilized sigmadelta ADC structures bk9 and bk18 not only can achieve the same function as the conventional sigmadelta ADC, but also can remove the circuit lowfrequency noises so as to increase the resolution of the converter.
The two abovedescribed structures of the present invention can be implemented by the switchedcapacitor circuit. Three application circuit examples are described hereinafter for reference. It should be noted that the control signals of all circuits in the drawings are shown in Fig. 4, and include six control clocks 1, 2, 11, 12, 21, 22.
The period T shown in Fig. 4 corresponds to the system sampling frequency of the structures of the present invention. Referring to Fig. 4, the clocks 1 and 2 have the same sampling period T, and are not overlapped with each other. The clocks 11 and 12 have the same sampling period 2T, and are not overlapped with each other while overlapped with the clock 1. The clock 21 and 22 have the same sampling period 2T, and are not overlapped with each other while overlapped with the clock 2. It should be also noted that all blocks A/D in the three examples can be implemented by a comparator, and all blocks D/A can be implemented by a positive/negative voltage output controlled by a onebit 16 digital signal. The circuit examples of the other building blocks are shown in Figs. 5(a) to 5(c), 6(a), 6(b), 7(a), and 7(b). In these figures, there are shown the conventional circuit examples, the circuit examples designed for the present invention, and the zdomain symbols of all building block circuits. For example, Fig. 7(a) shows a conventional switchedcapacitor differentiator, Figs. 5(c) and 6(b) show two switchedcapacitor chopper integrators ck25 and ck26 of the present invention, and Fig. 7(b) shows a switchedcapacitor chopper differentiator ck27. Since these circuits are clear to those skilled in the are, it is deemed unnecessary to be described further.
With reference to Fig. 8, there is shown a 1order chopperstabilized sigmadelta ADC structure bk30 with Z 1/(1+Z1) as building block, designed on the basis of the chopperstabilized sigmadelta ADC structure bkg of the present invention as shown in Fig. 2(a). Fig. 9 shows a fullydifferential 1order onebit chopperstabilized sigma delta ADC circuit cM with Z1/(1+Z1) as building block, designed on the basis of the structure bk30 of Fig. 8. The blocks bk27, bk28, and bk29 in the structure bk30 of Fig. 8 correspond to the circuit blocks ckl, ck2, and ck3 in the circuit cM of Fig. 9, respectively. The building block bk22 in the structure bk30 of Fig. 8 may be implemented by the circuit ck26 shown in Fig. 6(b). The block bk27 may be implemented by using the clocks 11 and 12 to control the differential signals, as shown in Fig. 9. The block bk29 17 may be implemented by using the clocks 11 and 12 to control the positive logic (Q) and negative logic (Q) of the comparator cpl, as shown in Fig. 9.
With reference to Fig. 10, there is shown a 1order chopperstabilized sigmadelta ADC structure bk42 with Z1/(1+Z1) as building block, designed on the basis of the chopper stabilized sigmadelta ADC structure bk18 of the present invention shown in Fig. 3(a). Fig. 11 shows a singleinputtosingleoutput 1order one bit chopper stabilized sigmadelta ADC circuit ck8 with z1/(1+Z1) as building block, designed on the basis of the structure bk42 of Fig. 10. The blocks bk39, bk40, and bk41 in the structure bk42 of Fig. 10 correspond to the circuit blocks ckS, ck6, and ck7 in the circuit ck8 of Fig. 11, respectively. The building block bk34 in the structure bk42 of Fig. 10 may be implemented by the circuit ck25 shown in Fig. 5(c). the block bk39 may be implemented by using the blocks 11 and 12 to control the differdntial signals, as shown in Fig. 11. The block bk41 may be implemented by using the clocks 11 and 12 to control the positive logic (Q) and negative logic (Q) of the comparator cp2, as shown in Fig. 11.
With reference to Fig. 12, there is shown a 2order chopperstabilized sigma"delta ADC structure bk57 with Z1/(1+Z1) as building block, designed on the basis of the chopper stabilized sigmadelta ADC structure bk9 of the present invention shown in Fig. 2. Fig. 13 shows a fully 18 differential 2order onebit chopperstabilized singledelta ADC circuit ck12 with Z1/(1+Z1) as building block, designed on the basis of the structure bk57 of Fig. 12. The blocks bk54, bk55, and bk56 in the structure bk57 of Fig. 12 correspond to the circuit blocks ck9, cklO, and ck11 in the circuit ck12 of Fig. 13, respectively. The building blocks bk46 and bk49 in the structure bk57 of Fig. 12 may be implemented by the circuit ck26 shown in Fig. 6(b). The block bk54 may be implemented by using the clocks 11 and 12 to control the differential signals, as shown in Fig. 13. The block bk56 may be implemented by using the clocks 11 and 12 to control the positive logic(Q) and negative logic (Q) of the comparator cp3, as shown in Fig. 13.
Of course, a variety of structures and circuits in addition to the abovedescribed examples may be designed on the basis of the chopperstabilized sigmadelta ADC structure bk9 or bk18 of the present invention. For example, the singleinputtosingleoutput 2order onebit chopperstabilized sigmadelta ADC with Z1/(1+Z1) as building blocks; the fullydifferential 1order onebit chopperstabilized sigmadelta ADC with (1Z1) as building block; the fullydifferential 2order onebit chopper stabilized sigmadelta ADC with (1Z1) as building block; the fullydifferential 2order onebit chopperstabilized sigmadelta ADC with (1+Z1) as building block, and so on.
It should be understood that the gain of the circuits of the 19 present invention may be adjusted depending on the application requirements.
In order to verify the advantages of the present invention in removing the circuit lowfrequency noises and increasing the resolution of the converter, there are described hereinafter the simulation comparisons between the conventional circuits shown in Figs. 15 and 17, and the circuits of the present invention shown in Figs. 18 and 19.
The circuit of Fig. 15 is designed from the conventional 1order sigmadelta ADC structure of Fig. 14. An equivalent noise voltage source el needed by the simulation is added in front of the operational amplifier al shown in Fig. 15, and the simulation is achieved by use of the switchedcapacitor circuit simulator software SWICAP2 developed by K. Suyana and S. C. Fang of Columbia University, U.S.A. The input signal is a sinusoidal wave_ with the frequency 1OkHz, and the sampling frequency is 1024 KHz. There are 4096 output signals sampled for spectrum analysis. When the noise source el equals to zero, i.e. in a noise free condition, the simulation result is plotted in Fig. 20(a) in solid line. When the noise source el is a 1 kHz sinusoidal wave, i.e. in a noisy condition, the simulation result is plotted in Fig. 20(a) in phantom line. It can be clearly seen from Fig. 20(a) that the output signal is contaminated by the lowfrequency noise. Fig. 18 is similar to Fig. 9, but an equivalent noise voltage source el is added in front of the operational amplifier a4. Using the same parameters and conditions as above, the simulation results are plotted in Fig. 20(b). It can be clearly seen from Fig. 20(b) that the simulation results are almost the same in both noise free and noisy conditions. Therefore, the immunity from the contamination of the lowfrequency noise is verified in the circuit of the present invention.
The circuit of Fig. 17 is designed from the conventional 2order sigmadelta ADC structure of Fig. 16. Two equivalent noise voltage sources el and e2 needed by the simulation are added respectively in front of the operational amplifiers a2 and a3 shown in Fig. 17, and the simulation is achieved also be use of the switchedcapacitor circuit simulator software SWICAP2. The input signal is a sinusoidal wave with the frequency 10 kHz, and the sampling frequency is 1024 kHz. There are 4096 output signals sampled for spectrum analysis. When both of the noise sources el and e2 equal to zero, i.e. in a noise free condition, the simulation result isplotted in Fig. 21(a) in solid line. When the noise source el is a 1 kHz sinusoidal wave, and the noise source e2 is a 4kHz sinusoidal wave, i.e. in s noisy condition, the simulation result is plotted in Fig. 21(a) in phantom line. It can be clearly seen from Fig. 21(a) that the output signal is contaminated by the lowfrequency noise. Fig. 19 is similar to Fig. 13, but two equivalent noise voltage sources el nd e2 are added respectively in fronts of the operational amplifiers a5 and a6. Using the same parameters and conditions as above, the 21 simulation results are plotted in Fig. 21(b). It can be clearly seen from Fig. 21(b) that the simulation results are almost the same in both of noise free condition and noisy condition. Therefore, the immunity from the contamination of the lowfrequency noise is verified again in the circuit of the present invention.
It has been verified from both theoretical derivation and computer simulation that the present invention is immune from the lowfrequency noise, so that the resolution of the sigmadelta ADC can be greatly increased. Thus, the present invention is very suitable to be applied to the highresolution(2: 16 bits) sigmadelta analogtodigital converter circuits.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.
22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Claims (10)
 What is claimed is: 1. A chopperstabilized sigmadelta analogtodigitalconverter (ADC) comprising:a first discretetime multiplier adapted to receive an analog input signal and a first discretetime sequence, and to multiply said analog input signal by said first discretetime sequence to produce a choppered analog signal; and a chopper sigmadelta analogtodigital converter (ADC) connected in series to said first discretetime multiplier in order to receive and convert said choppered analog signal into a digital output signal, said chopper sigmadelta ADC being characterized in zdomain by:Y1(z)=Xl(z) STI(z) + Q(z)NTI(z), z= ejw wherein STI(z) is a signal transfer function, and is characterized by having a passband in a highfrequency range; and NTI(z) is a noise transfer function, and characterized by having a high attenuation is said highfrequency range.
 2. A chopperstabilized sigmadelta ADC as claimed in claim 1, wherein said fist discretetime sequence is consisted of alternating 11111 and 11111 digital signals.
 3. A chopperstabilized sigmadelta ADC as claimed in claim 1, wherein said first discretetime sequence is consisted of alternating 11111 and 11011 digital signals.23 2 3
 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4. A chopperstabilized sigmadelta ADC as claimed in claim 2, further comprising a second discretetime multiplier connected in series to said chopper sigmadelta ADC in order to receive said digital output signal, said second discretetime multiplier adapted to receive a second discretetime sequence, and multiplying said digital output signal by said second discretetime sequence to produce a choppered digital signal.
 5. A chopperstabilized sigmadelta ADC as claimed in claim 4, wherein said second discretetime sequence is consisted of alternating 11111 and 11111 digital signals.
 6. A chopperstabilized sigmadelta ADC as claimed in claim 5, wherein said highfrequency range is an area around an angular frequency v.
 7. A chopperstabilized sigmadelta ADC as claimed in claim 3, further comprising a second discretetime multiplier connected in series to said chopper sigmadelta ADC in order to receive said digital output signal, said second discretetime multiplier adapted to receive a second discretetime sequence, and multiplying said digital output signal by said second discretetime sequence to produce a choppered digital signal.24 1
 8. A chopperstabilized sigmadelta ADC as claimed in claim 2 7, wherein said second discretetime sequence is consisted 3 of alternating "I" and 11111 digital signals.4 6 7 8
 9. A chopperstabilized sigmadelta ADC as claimed in claim 8, wherein said highfrequency range is an area around an angular frequency v.
 10. A chopperstablised sigmadelta analoguetodigital converter substantially in accordance with any embodiment hereinbefore described with reference to Figures 2a to 4, 5c, 6b, 7b to 13 and 18 to 21(b) of the accompanying drawings.
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GB9310144A GB2278247A (en)  19930517  19930517  Chopperstabilized sigmadelta converter 
DE19934318728 DE4318728C1 (en)  19930517  19930607  Chopper stabilised sigmadelta analogue=to=digital converter  has choppersigmadelta converter which receives chopped analogue signal from time discrete multiplier 
FR9306925A FR2706703A1 (en)  19930517  19930609  Sigmadelta analogue/digital converter stabilized by chopping 
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GB9310144A GB2278247A (en)  19930517  19930517  Chopperstabilized sigmadelta converter 
DE19934318728 DE4318728C1 (en)  19930517  19930607  Chopper stabilised sigmadelta analogue=to=digital converter  has choppersigmadelta converter which receives chopped analogue signal from time discrete multiplier 
FR9306925A FR2706703A1 (en)  19930517  19930609  Sigmadelta analogue/digital converter stabilized by chopping 
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Cited By (2)
Publication number  Priority date  Publication date  Assignee  Title 

US6201835B1 (en)  19990305  20010313  BurrBrown Corporation  Frequencyshaped pseudorandom chopper stabilization circuit and method for deltasigma modulator 
EP1569345A1 (en) *  20040228  20050831  Lucent Technologies Inc.  Bandpass deltasigma analogtodigital converters 
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GB9408686D0 (en) *  19940430  19940622  Smiths Industries Plc  Analogtodigital conversion systems 
DE19630605A1 (en) *  19960729  19980205  Tech Gmbh Antriebstechnik Und  Multiplication circuit for power meter 
US6172630B1 (en) *  19980818  20010109  Tektronix, Inc.  Extended common mode input range for a deltasigma converter 
DE10237126B4 (en) *  20020514  20170914  Ams Ag  Measuring circuit 
DE102008027939A1 (en) *  20080612  20091224  Rutronik Elektronische Bauelemente Gmbh  Analog / digital converter with a SAR topology and associated method 
Citations (1)
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US5179380A (en) *  19920207  19930112  Rockwell International Corporation  Onebit sigmadelta modulator with improved signal stability 
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JPH01233921A (en) *  19880315  19890919  Toshiba Corp  A/d conversion circuit using deltasigma modulator 
GB2256551B (en) *  19910606  19960124  Crystal Semiconductor Corp  Switched capacitor integrator with chopper stabilisation performed at the sampling rate 

1993
 19930517 GB GB9310144A patent/GB2278247A/en not_active Withdrawn
 19930607 DE DE19934318728 patent/DE4318728C1/en not_active Expired  Lifetime
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US5179380A (en) *  19920207  19930112  Rockwell International Corporation  Onebit sigmadelta modulator with improved signal stability 
Cited By (3)
Publication number  Priority date  Publication date  Assignee  Title 

US6201835B1 (en)  19990305  20010313  BurrBrown Corporation  Frequencyshaped pseudorandom chopper stabilization circuit and method for deltasigma modulator 
EP1569345A1 (en) *  20040228  20050831  Lucent Technologies Inc.  Bandpass deltasigma analogtodigital converters 
US7126516B2 (en)  20040228  20061024  Lucent Technologies Inc.  Bandpass deltasigma analogtodigital converters 
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GB9310144D0 (en)  19930630 
FR2706703A1 (en)  19941223 
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