KR0133499B1 - Sigma-delta analog digital converter - Google Patents

Abstract

The chopper stabilized sigma-delta analog-to-digital converter according to the present invention receives an analog input signal and a first discrete time sequence and multiplies the analog input signal by the first discrete time sequence to generate a choppered analog signal. A discrete time multiplier is provided. Chopper sigma-delta analog-to-digital converters are connected in series with discrete time multipliers to receive the chopper analog signals and convert them into digital output signals. Chopper Sigma-Delta Analog-to-Digital Converters

Y '(z) = X' (z) ST '(z) + Q (z) NT (z), z = e ^jw

In this case, ST '(z) is characterized by having a pass band in the high frequency region as a signal transmission function, NT' (z) is characterized by having a high attenuation in the high frequency region as a noise transmission function do. In this way, circuit low frequency noise is removed to increase the resolution of the converter.

Description

Chopper Stabilized Sigma-Delta Analog Digital Converters

1 (a) to (e) are views showing the structure and characteristics of a sigma-delta analogue-to-digital converter according to the prior art.

2 (a) to 2 (h) show the structure and characteristics of the chopper-stabilized sigma-delta analogue-digital converter according to the first preferred embodiment of the present invention, which is suitable for the configuration of the whole differential circuit. drawing.

3 shows the structure and characteristics of a chopper stabilized sigma-delta analogue-to-digital converter according to a second preferred embodiment of the present invention suitable for the construction of a single-input to single-output circuit.

4 shows the control clock shown in all schematic diagrams of the figure.

5 (a) and 5 (b) are circuit diagrams of z-area symbols and two types of single-input to single-output building blocks according to the prior art.

5 (c) is a circuit diagram of a z-region symbol and a single-input to single-output building block in accordance with the present invention.

Fig. 6 (a) is a circuit diagram of a z-region symbol and whole differential building block according to the prior art.

6 (b) is a circuit diagram of a z-region symbol and whole differential building block according to the present invention.

Fig. 7 (a) is a circuit diagram of a z-region symbol and gain building block according to the prior art.

7 (b) is a circuit diagram of a z-region symbol and gain building block according to the present invention.

FIG. 8 is a block diagram of a first-order chopper stabilized sigma-delta analogue-to-digital converter designed based on the structure shown in FIG. 2 and having Z ⁻¹ / (1 + Z ⁻¹ ) as the building block.

FIG. 9 is designed based on the structure shown in FIG. 8, and is a schematic of a full differential first-order 1-bit chopper stabilized sigma-delta analogue-to-digital converter having Z ⁻¹ / (1 + Z ⁻¹ ) as a building block. Electrical block diagram.

FIG. 10 is a block diagram of a first-order chopper stabilized sigma-delta analogue-to-digital converter designed based on the structure shown in FIG. 3 and having Z ⁻¹ / (1 + Z ⁻¹ ) as the building block.

FIG. 11 is designed based on the structure shown in FIG. 10 and is a single-input to single-output 1-order 1-bit chopper stabilized sigma-delta analog with Z ⁻¹ / (1 + Z ⁻¹ ) as building blocks. -Block diagram of the digital converter.

FIG. 12 is a block diagram of a two-order chopper stabilized sigma-delta analogue-to-digital converter designed based on the structure shown in FIG. 2 and having Z ⁻¹ / (1 + Z ⁻¹ ) as the building block.

FIG. 13 is designed based on the structure shown in FIG. 12 and is a schematic of a 2nd order 1-order 1-bit chopper stabilized sigma-delta analog-to-digital converter with Z ⁻¹ / (1 + Z ⁻¹ ) as a building block. Electrical block diagram.

14 is a block diagram of a first-order sigma-delta analogue-to-digital converter according to the prior art.

FIG. 15 is a schematic electrical block diagram of a first-order sigma-delta analogue-to-digital converter, designed based on the structure shown in FIG. 14, with one operating noise source added.

16 is a block diagram of a two-order sigma-delta analogue-to-digital converter according to the prior art.

FIG. 17 is a schematic electrical block diagram of a two-order sigma-delta analogue-to-digital converter according to the prior art, designed based on the structure shown in FIG. 16, with the addition of two equivalent noise sources.

FIG. 18 is similar to FIG. 9, but with one equivalent noise source added in accordance with the present invention.

19 is similar to FIG. 13 but with two equivalent noise sources added in accordance with the present invention.

20 (a) and 20 (b) show simulation spectra of the circuits shown in FIGS. 15 and 18. FIG.

21 (a) and 21 (b) show simulation spectra of the circuits shown in FIGS. 17 and 19. FIG.

FIELD OF THE INVENTION The present invention relates to analog-to-digital converters (ADCs) and in particular uses chopper stabilizers to increase the resolution of sigma-delta analog converters by removing circuit low frequency noise. Chopper stabilized sigma-delta analog-to-digital converter.

Today, the interface circuits of sigma-delta analogue-to-digital converters are widely used for applications in ultra-large scale integrated circuits (VLSI). For example, for telecommunications products, the interface circuit of the sigma-delta analog-to-digital converter may be an integrated services digital network (ISDN) U-interface, 9600 modem (modem V.32 9600 bps), pulse code modulation code. It is applied to a decoder (pulse code modulation code decoder, PCM codec). In consumer electronics, the interface circuit of the sigma-delta analogue-to-digital converter is applied to digital audio tape (DAT) recorders, compact disc (CD) player systems and the like. In metrology applications, the interface circuit of the sigma-delta analogue-to-digital converter is applied to 51/2 digital panel instruments capable of resolving 1kHz signals. In such a system, it is necessary to design different digital signal processing (DSP) chips, which are connected to the sigma-delta analog-to-digital converter, differently as needed to satisfy the requirements of different implementations. Therefore, it can be seen that sigma-delta analogue-to-digital converters are applied to various integrated circuit applications.

14 and 15, a sigma-delta analogue-to-digital converter according to the prior art is typically configured by a switched-capacitor such as a switch. The technique is described in detail in the Oversampled Sigma-Delta Data Converter presented by SR Norsworth at the ISCAS'90 Workshop in New Orleans, Louisiana, April 30, 1990. It is. Sigma-delta analogue-to-digital converters are discrete-time systems, and the relationship between inputs and outputs is represented in the z-domain. Where z = e ^jw and w is the angular frequency. The relationship between the angular frequency w and the continuous signal frequency f is represented by w = 2πf / f ^3, where f ³ is the sampling frequency of the system. Where sampling frequency f ³ = 1 / T, where T is the sampling period. In multi-frequency signal f = f ^3/2, f is an angular frequency π. In this specification, the representations for the sigma-delta analogue-to-digital converter are all made in the z-domain.

1 (a) to 1 (e) show a sigma-delta analogue-digital converter 1 according to the prior art, and the transfer function of the sigma-delta analogue-digital converter 10 in the z-domain is Y (z) = X (z) ST (z) + Q (z) NT (z), z = e ^jw where ST (z) is the transfer function and NT (z) is the noise transfer function to be. As shown in FIG. 1 (b), the signal transfer function ST (z) has a pass band for passing the input low frequency in the low frequency region. In Fig. 1 (c), the noise transfer function NT (z) has a very high attenuation in the low frequency region, which is generated when the input signal passes through the analog-to-digital converter ADC of the sigma-delta analog-to-digital converter 10. Attenuates most of the low frequency quantization noise. The ADC is a low-bit analog-to-digital converter and typically only outputs one bit. In this way, the quantization noise is not large enough to interfere with the passage of the normal signal in the low frequency region. As shown in Figures 1 (d) and 1 (e), the quantization noise generated when the input signal X passes through the sigma-delta analog-to-digital converter 10 is very small in the low frequency region. However, because the signal transfer function ST (z) has a passband in the low frequency region, other circuit low frequency noises except quantization noise, such as 1 / f noise and the offset voltage of the op amp, are normal low frequency signals. At the same time, passing through the sigma-delta analog-to-digital converter 10 affects the output digital signal y. Therefore, the circuit low frequency limits that the sigma-delta analogue-to-digital converter 10 has a high resolution of, for example, 16 bits or more.

Known methods for reducing low frequencies in sigma-delta analog-digital converter circuits are, for example, replacing op amps with chopper stabilized op amps or correlated double sampling methods, such as typical switched capacitor circuits. It is generally derived from a method of reducing low frequency noise in the interior. See US Pat. No. 4,939,516 for a method of replacing an operational amplifier with a chopper stabilization circuit. Both of these methods solve this low-frequency noise problem from the circuit's point of view, so that only a fraction of this noise problem can be solved.

14 to 17 show a typical sigma-delta analogue-to-digital converter according to the prior art. FIG. 14 shows a 1-order sigma-delta analogue-to-digital converter, and FIG. 15 shows a circuit designed based on the structure shown in FIG. FIG. 16 shows a single-input to single-output two-order 1-bit sigma-delta analogue-to-digital converter, and FIG. 17 shows a circuit designed based on the structure shown in FIG. The block of Z ⁻¹ / (1 + Z ⁻¹ ) may be performed by the circuit shown in FIG. 5 (b). The structures and circuits shown in FIGS. 5 (b) and 14-17 are obvious to those skilled in the art, and further descriptions thereof will be omitted. Other conventional sigma-delta analogue-to-digital converters are described in US Pat. No. 5,068,660; 4,983,975; 4,972,436; 4,972,360; 4,939,516; Or similar methods as disclosed in US Pat. No. 4,920,544.

It is an object of the present invention to provide a chopper stabilized sigma-delta analogue-to-digital converter to solve the low frequency noise problem mentioned above to increase the resolution of the sigma-delta analogue-to-digital converter. The present invention approaches this problem from the perspective and description of the system, which is different from the perspective of the circuit in the prior art.

It is another object of the present invention to provide a chopper stabilized sigma-delta analogue-to-digital converter with a simple circuit configuration that is easy to design and does not require any special fabrication process.

The chopper stabilized sigma-delta analogue-to-digital converter according to the present invention receives an analog input signal and a first discrete time sequence and multiplies the analog input signal by the first discrete time sequence to obtain a choppered analog signal. A chopper sigma-delta analog-digital converter in series with the first discrete time multiplier for receiving and converting the chopper analog signal to a digital output signal; The digital transducer is in the Z zone

Y '(z) = X' (z) ST '(z) + Q (z) NT (z), z = e ^jw

In this case, ST '(z) is characterized by having a pass band in the high frequency region as a signal transmission function, NT' (z) is characterized by having a high attenuation in the high frequency region as a noise transmission function Chopper stabilized sigma-delta analog-to-digital converter.

In another aspect of the invention, a chopper stabilized sigma-delta analogue-to-digital converter comprises a second discrete time multiplier in series with the chopper sigma-delta analogue-to-digital converter for receiving the digital output signal. The discrete time multiplier receives a second discrete time sequence and multiplies the digital output signal by a second discrete time sequence to generate a chopper digital signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the description of the present invention, two types of chopper stabilized sigma-delta analogue-to-digital converters are disclosed. FIG. 2 (a) shows a first type of chopper stabilized sigma-delta analogue-to-digital converter bk9 suitable for whole differential circuit configuration as a preferred best embodiment. FIG. 3 (a) shows a second type of chopper stabilized sigma-delta analogue-to-digital converter bk18 suitable for single-input to single-output circuit configuration as a second preferred embodiment.

First embodiment (best embodiment)

Referring to FIG. 2 (a), the chopper stabilized sigma-delta analogue-to-digital converter bk9 according to the first preferred embodiment of the present invention is a discrete time multiplier bk1 connected in series, the chopper sigma-delta analogue-digital converter bk3 and also Another discrete time multiplier bk4 is provided. Discrete time multiplier bk1 receives a discrete time sequence bk2 consisting of an alternating 1 and -1 digital signal with an input analog low frequency signal x and multiplies the input analog low frequency signal x with a discrete time sequence bk2 to generate a signal x '.

The chopper sigma-delta analogue-to-digital converter bk3 specially designed by the present invention receives the discrete time multiplier bk1 and receives the output signal x 'and converts it to the digital signal output y'. The discrete time multiplier bk4 receives the discrete signal sequence bk5 consisting of the output signal y 'of the chopper sigma-delta analogue-digital converter bk3 and alternating 1 and -1 digital signals, and to the full chopper stabilized sigma-delta analogue-digital converter bk9. The output signal y 'is multiplied by the discrete time sequence bk5 to generate a digital output signal y for the signal.

2 (a) to 2 (h), FIG. 2 (b) to FIG. 2 (d) show the characteristics of the chopper-stabilized sigma-delta analogue-to-digital converter bk3. e) to (h) are schematic diagrams of the semi-spectrum of each signal at different points in the chopper stabilized sigma-delta analogue-to-digital converter bk9. The multiplication operation performed by the discrete time multiplier bk1 is called a chopper operation and centers the input low frequency signal x having the center frequency at w _x at (π + w _x ) as shown in FIG. 2 (e). It can be modulated with a signal having a frequency, which is represented by a signal x 'having a center frequency at (π + w _x ) as shown in FIG. The transfer function of the chopper sigma-delta analogue-to-digital converter bk3 in the z region is expressed as Y '(z) = X' (z) ST '(z) + Q (z) NT (z), z = e ^jw Where ST '(z) is a signal transfer function and NT' (z) is a noise transfer function. As shown in FIG. 2 (c), the signal transmission function ST '(z) is a high-frequency signal, i.e., a signal near the angular frequency π, so as to pass a pass band in the high-frequency region, that is, in the vicinity of each frequency π. It is characterized by having. As shown in Fig. 2 (d), the noise transfer function NT '(z) is an analog-to-digital converter A / D of the chopper sigma-delta analogue-to-digital converter bk3 (A / D is a low bit analogue-digital). It is a converter, and typically outputs only 1 bit.) It has a very high attenuation in the high frequency region in order to attenuate most of the quantization noise in the high frequency generated when passing through. In this way, the quantization noise does not increase in the high frequency region enough to interfere with the signal passage of a normal high frequency signal. Figure 2 (g) shows the spectrum showing that the output digital signal y 'is the circuit low frequency noise combined at this time. The chopper multiplication of bk4 of the discrete time multiplier chops the output signal y 'of the chopper sigma-delta analog-digital converter bk3 to finally output the desired signal y. The spectrum of the digital signal y is shown in Figure 2 (h).

In this way, there is only very little quantization noise in the low frequency region, and the circuit low frequency noise is chopped into the high frequency region by the chopper multiplication of the discrete time multiplier bk4 so as not to affect the resolution. Since both the input signal and the output signal of the discrete time multiplier bk4 are digital, the discrete time multiplier bk4 can be designed in a digital signal processing chip connected to the sigma-delta analogue-to-digital converter. That is, the chopper-stabilized sigma-delta analogue-to-digital converter bk9 according to the present invention does not have to have a discrete time multiplier bk4.

Second embodiment

Referring to FIG. 3 (a), the chopper stabilized sigma-delta analogue-to-digital converter bk18 according to the second preferred embodiment of the present invention is a discrete time multiplier bk10 connected in series, the chopper sigma-delta analogue-digital converter bk12 and also Another discrete time multiplier bk13 is provided. Discrete time multiplier bk10 receives a discrete time sequence bk11 consisting of alternating 1 and 0 signals with an input analog low frequency signal x and multiplies the input analog low frequency signal x with a discrete time sequence bk11 to generate a signal x '. The chopper sigma-delta analogue-digital converter bk12 specifically designed by the present invention receives the output signal x 'of the discrete time multiplier bk10 and converts it into a digital signal output y'. Discrete time multiplier bk13 receives the discrete signal sequence bk14, consisting of alternating 1 and -1, with the output signal y 'of the chopper sigma-delta analog-digital converter bk12, and digital for the full chopper-stabilized sigma-delta analog-digital converter bk18. The output signal y 'is multiplied by the discrete time sequence bk14 to generate the output signal y. Referring to FIGS. 3 (a) to 3 (h), FIGS. 3 (b) to 3 (d) show the characteristics of the chopper stabilized sigma-delta analogue-to-digital converter bk12. e) through (h) are schematic diagrams of the semi-spectrum of each signal at different points in the chopper stabilized sigma-delta analogue-to-digital converter bk18. The chopper operation performed by the discrete time multiplier bk10 receiving the discrete time sequence bk11 is performed by the discrete time multiplier bk1 receiving the discrete time sequence bk2 as shown in FIG. 2 (a). ) And a slightly different result. Discrete time multiplier bk10 is represented by a signal having a center frequency at (π + w _x ) as only the half of the input low frequency signal x having a center frequency at w _x as shown in FIG. 3 (e). On the other hand, as shown in FIG. 3 (f), the other half of the input signal x still remains in the low frequency region. The transfer function of the chopper-stabilized sigma-delta analogue-to-digital converter bk12 in the z region is expressed as Y '(z) = X' (z) ST '(z) + Q (z) NT (z), z = e ^jw Where ST '(z) is a signal transfer function and NT' (z) is a noise transfer function. As shown in FIG. 3 (c), the signal transmission function ST '(z) has a pass band in the high frequency region so that an input high frequency signal can pass. As shown in Figure 3 (d), the noise transfer function NT '(z) is the analog-to-digital converter A / D of the input signal chopper sigma-delta analog-to-digital converter bk12 (A / D is a low-bit analog-to-digital converter). In order to attenuate most of the quantization noise in the high frequency generated when passing only one bit), it has a very high attenuation amount in the high frequency region. In this way, the quantization noise is not large enough to interfere with the passage of the normal high frequency signal. Figure 3 (g) shows the spectrum showing that the output digital signal y 'and the circuit low frequency noise are then combined. The chopper multiplication of bk13 of the discrete time multiplier choppers the output signal y 'of the chopper sigma-delta analogue-digital converter bk12 to output the final digital signal y. The spectrum of the digital signal y is shown in Figure 3 (h). In this way, there is only very little quantization noise in the low frequency region, and the circuit low frequency noise is choppered into the high frequency region by the chopper multiplication of the discrete time multiplier bk13 so as not to affect the resolution. In addition, 0.5-time linear error in this embodiment is because only half of the low frequency signal x is shifted to the high frequency region, i.e., 1/2 is attenuated before the low frequency signal x undergoes the analog-to-digital conversion process. Will be. However, this linear error is then compensated for in the digital signal processing chip. Since both the input signal and the output signal of the discrete time multiplier bk13 are digital, the discrete time multiplier bk13 can be designed in a digital signal processing chip connected with a sigma-delta analogue-digital converter. In other words, the chopper stabilized sigma-delta analogue-to-digital converter bk18 according to the present invention does not have to have a discrete time multiplier bk13.

In summary, the chopper stabilized sigma-delta analogue-to-digital converter bk19 according to the first embodiment of the present invention is a function within the z region.

Y (z) = X (z) ST (z) + Q (z) NT (z), z = e ^jw

Is displayed. That is, the same transfer function as that of the sigma-delta analog-digital converter according to the prior art is obtained. The function of the chopper-stabilized sigma-delta analogue-to-digital converter bk18 according to the second embodiment of the present invention is in the z region.

Y (z) = 0.5X (z) ST '(z) + Q (z) NT (z), z = e ^jw

Is displayed. This also yields the same transfer function as the sigma-delta analog-to-digital converter of the prior art, except for a 0.5-time linear error. As mentioned above, this linear error can be compensated for in the digital signal processing chip. Therefore, the chopper stabilized sigma-delta analogue-digital converters bk9 and bk18 not only obtain the same function as the sigma-delta analogue-digital converters of the prior art but also control the circuit low frequency noise to greatly increase the resolution of the converter.

The two structures according to the present invention described above can be performed by a switched capacitor. Examples of three application circuits are described below. Note that the control signals of all circuits in the figure are shown in FIG. 4 and include six control clocks 1, 2, 11, 12, 21, 22.

The period T shown in FIG. 4 corresponds to the system sampling frequency of the device according to the invention. Referring to FIG. 4, clocks 1 and 2 have the same sampling period T and do not overlap each other. Clocks 11 and 12 have the same sampling period sT and do not overlap each other, but overlap with clock 1. Clocks 21 and 22 have the same sampling period 2T and do not overlap each other, but overlap with clock 2. In three examples all block A / Ds may be performed by a comparator, while all block D / As may be performed by a negative / positive voltage output controlled by a 1-bit digital signal. Circuit examples of the other blocks are shown in Figs. 5 (a) to 5 (c), 6 (a), 6 (b) and 7 (a). In this figure, the example of the circuit according to the prior art, the design circuit example for the present invention, and the z area symbol of the circuit of all the building blocks are shown. For example, Figure 7 (a) shows a switched capacitor differentiator according to the prior art, and Figures 5 (c) and 6 (b) show two switched capacitor chopper integrators ck25 and ck26 according to the present invention. 7 (b) shows the switched capacitor chopper differentiator ck27. Such circuits are obvious to those skilled in the art and will not be described in further detail.

Referring to FIG. 8, a first-order chopper stabilized sigma-delta analogue-to-digital converter bk30 designed based on the chopper-stabilized sigma-delta analogue-to-digital converter bk9 according to the present invention shown in FIG. 2 (a) is shown. have. FIG. 9 shows a full differential first-order 1-bit chopper-stabilized sigma-delta analog-to-digital converter ck4 designed based on bk30 in FIG. 8 and having Z ⁻¹ / (1 + Z ⁻¹ ) as the building block. Blocks bk27, bk28 and bk29 in bk30 in FIG. 8 correspond to circuit blocks ck1, ck2 and ck3 in circuit ck4 in FIG. The building block bk22 in bk30 of FIG. 8 can be performed by the circuit ck26 shown in FIG. 6 (b). As shown in FIG. 9, block bk27 can be performed by using clocks 11 and 12 to control the differential signal. As shown in FIG. 9, block bk29 may be performed by using clocks 11 and 12 to control the comparator cp1 positive logic Q and negative logic t1.

Referring to FIG. 10, designed based on the chopper stabilized sigma-delta analogue-to-digital converter bk18 according to the present invention shown in FIG. 3 (a), Z- ¹ / (1 + Z- ¹ ) as a building block. The branch shows a 1-order 1-bit chopper stabilized sigma-delta analogue-to-digital converter bk8. FIG. 11 shows a single input single output 1-order 1-bit 1-bit chopper stabilized sigma-delta analog-to-digital converter bk8 designed based on bk42 in FIG. 10 and having Z ⁻¹ / (1 + Z ⁻¹ ) as the building block. have. Circuit blocks bk39, bk40 and bk41 in the circuit ck8 in FIG. 11 in FIG. 11 of bk42 correspond to circuit blocks ck5, ck6 and ck7 in the circuit ck8 in FIG. The building block bk34 in bk42 of FIG. 10 can be performed by the circuit ck25 shown in FIG. 5 (c). As shown in FIG. 11, block bk39 may be performed by using clocks 11 and 12 to control the differential signal. As shown in FIG. 11, block bk41 can be performed by using clocks 11 and 12 to control the positive logic Q and negative logic t2 of comparator cp2.

Referring to FIG. 12, it is designed based on the chopper-stabilized sigma-delta analogue-to-digital converter bk9 according to the present invention shown in FIG. 2 and has a building block with Z ⁻¹ / (1 + Z ⁻¹ ). An order chopper stabilized sigma-delta analogue-to-digital converter bk57 is shown. FIG. 13 shows a full differential 2-order 1-bit chopper stabilized sigma-delta analogue-to-digital converter circuit ck12 designed based on bk57 in FIG. 12 and having Z ⁻¹ / (1 + Z ⁻¹ ) as the building block. . Blocks bk54, bk55 and bk56 in bk57 in FIG. 12 correspond to circuit blocks ck9, ck10 and ck11 in circuit ck12 in FIG. The building blocks bk46 and bk49 in bk57 in FIG. 12 can be performed by the circuit ck26 shown in FIG. 6 (b). As shown in FIG. 13, block bk54 may be performed by using clocks 11 and 12 to control the differential signal. As shown in FIG. 31, block bk56 can be performed by using clocks 11 and 12 to control the positive logic Q and negative logic t3 of comparator cp3.

Of course, in addition to the examples described above, various devices and circuits can be designed based on the chopper stabilized sigma-delta analogue-to-digital converter bk9 or bk18 according to the present invention. For example, a single input single output two-order 1-bit chopper stabilized sigma-delta analogue-to-digital converter with Z ^-1 / (1 + Z ^-1 ) as the building block, (1-Z ^-1 ) as the building block. stabilize before differential chopper 2-order one bit having a sigma-delta analog-to-digital converter and building blocks as (1 + Z ^-1) with the pre-order derivative 2-bit chopper stabilized sigma-delta analog-to-digital converter including a design to be Can be. Here, although the circuit gain of the ADC according to the present invention is not specified, the above-described circuit gain can be properly adjusted to high gain or low gain without departing from the spirit of the invention according to the requirements of the required circuit design. It is obvious to those skilled in the art. In order to demonstrate the advantages of the present invention to remove circuit low frequency noise and increase the resolution of the converter, the circuits according to the prior art shown in FIGS. 15 and 17 and the present invention shown in FIGS. The simulation comparison between the circuits will be described next.

The circuit of FIG. 15 is designed from the first-order sigma-delta analogue to digital converter shown in FIG. One equivalent noise source e1 required by the simulation is added to the tip of the operational amplifier a1 shown in FIG. 15, and the simulation is SWICAP2, a switched capacitor simulation software developed by K. Suyama and SC Fang of Columbia University. Is performed using The input signal is a sine wave with a frequency of 10KHz and the sampling frequency is 1024KHz. There are 4069 sampled output signals for spectral analysis. If the noise source e1 is 0, i.e., in a noisy condition, the simulation result is indicated by the thick line in FIG. 20 (a). If the noise source e1 is a 1 KHz sine wave, i.e., a noise condition, the simulation result is indicated by a dotted line in Fig. 20 (a). It is clear from Fig. 20 (a) that the output signal is affected by low frequency noise. 18, an equivalent noise voltage source e1, similar to that of FIG. 9, is added to the tip of operational amplifier a4. Simulation results using the same parameters and conditions as above are shown in FIG. 20 (b). It can be clearly seen from FIG. 20 (b) that the simulation results in the noise and noise conditions are almost the same. It is therefore demonstrated in the circuit according to the invention that it can escape from the effects of low frequency noise.

The circuit of FIG. 17 is designed from a two-order chopper stabilized sigma-delta analogue-to-digital converter according to the prior art shown in FIG. Two equivalent noise sources e1 and e2 required by the simulation are added to the front ends of the operational amplifiers a2 and a3 respectively shown in FIG. 17, and the simulation is also performed using the switched capacitor simulator software SWICAP 2 described above. The input signal is a sine wave with a frequency of 10KHz and the sampling frequency is 1024KHz. There are 4069 sampled output signals for spectral analysis. When the noise sources e1 and e2 are zero, i.e., no noise condition, the simulation result is indicated by the thick line in Fig. 21 (a). If the noise source e1 is a 1 KHz sine wave and the noise source e2 is a sine wave of 4 KHz, that is, the noise condition, the simulation result is indicated by the dotted line in Fig. 21 (a). From Fig. 21 (a) it is clear that the output signal is affected by low frequency noise. 19 is similar to FIG. 13 except that equivalent noise voltage sources el and e2 are added to the leading ends of operational amplifiers a5 and a6, respectively. Simulation results using the same parameters and conditions as above are shown in FIG. 21 (b). It can be clearly seen from FIG. 21 (b) that the simulation results in the noise-free and caught conditions are almost the same. Therefore, the deviation from the influence of frequency noise is demonstrated in the circuit according to the present invention.

Therefore, as can be seen from the above simulation results and the above description, the sigma-delta ADC circuit of the present invention can not only be free from the effects of undesirable low frequency noise, but also preferably the resolution in the ADC circuit. It will be appreciated that it can be increased. The invention is also suitable for the application of high resolution (≧ 16 bits) sigma-delta analogue-to-digital converter circuits.

It should be noted that the foregoing is a description of the most practical and optimal embodiments of the present invention and is not limited only to those disclosed herein. Therefore, it will be apparent to those skilled in the art that various embodiments are possible in addition to the above embodiments without departing from the spirit and scope of the claims.

Claims (4)

In a chopper-stabilized sigma-delta analogue-to-digital converter, an analog input signal (X) and first discrete time sequence signals bk2 and bk11 are inputted to multiply the first discrete time sequence signal by the analog input signal to provide a chopper analogue. First discrete time multipliers bk1 and bk10 for outputting a signal X 'The first discrete time multipliers bk1 and bk10 may be used to input the chopper analog signal X' and convert it to a digital output signal Y '. bk10), a chopper sigma-delta analog-digital converter connected in series with the chopper sigma-delta analog-digital converter, Y '(z) = X' (z) ST '(z) + Q (z) NT (z), z = e ^jw Where ST '(z) is a signal transfer function and has a pass band in the high frequency region corresponding to the region near π at an angular frequency, and NT' (z) is a noise transfer function in the high frequency region. Connected in series with the chopper sigma-delta analog-digital converters bk3, bk12 and the digital output signal Y 'configured to have attenuation amounts in series to receive the chopper sigma-delta analog-digital converters bk3, bk12. And a second discrete time multiplier (bk4, bk13) for outputting the chopper digital signal (Y) by multiplying the two discrete time sequence signals (bk5, bk14) by the digital output signal (Y '). Sigma-Delta Analog-to-Digital Converter. 2. The chopper-stabilized sigma-delta analogue-to-digital converter according to claim 1, wherein the first discrete time sequence signal consists of alternating 1 and -1 digital signals. The chopper-stabilized sigma-delta analog-to-digital converter according to claim 1, wherein the first discrete time sequence signal consists of alternating 1 and 0 digital signals. 2. The chopper-stabilized sigma-delta analog-to-digital converter according to claim 1, wherein the second discrete time sequence signal consists of alternating 1 and -1 digital signals.