JPH08162961A - A/d converter - Google Patents

Abstract

PURPOSE: To provide an A/D converter capable of canceling offset by simple constitution. CONSTITUTION: A comb filter 5 is constituted of a differentiation circuit composed of a RAM 21 and subtractors 22 and 23 and an integration circuit composed of registers 24 and 25 and an adder and computes and outputs the moving average of bit string data oversampled by a ΔΣ modulation circuit 4 and quantized to one bit. Based on data for which a reference voltage Vref is oversampled, the offset data of the AE modulation circuit 4 outputted through the comb filter 5 and an FIR filter 6 are stored as the initial value of the integration circuit in the register 25 for constituting the integration circuit at the final stage of the comb filter 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to offset cancellation of an oversampling A / D converter.

[0002]

2. Description of the Related Art FIG. 4 is a block circuit diagram of a conventional oversampling A / D converter (hereinafter, simply referred to as an A / D converter).

The analog signal Ain input to the A / D converter 51 is input to a ΔΣ (delta sigma) modulation circuit 52. The ΔΣ modulation circuit 52 receives the input analog signal A
Sampling is performed based on clock signals φ ₁ and φ ₂ having a frequency of several tens to several hundreds times the signal frequency of in. And ΔΣ
The modulation circuit 52 is adapted to generate bit string data by quantizing the sampled data into 1 bit and output it to the digital filter 53.

The digital filter 53 is a decimation filter, and includes a comb filter 54 and an FIR filter 5.
5, the input bit string data is subjected to decimation processing and the processing result is output as digital data Dout.

That is, as shown in FIG. 6, the comb filter 54 includes a quadratic differentiating circuit 64 including a RAM (Random Access Memory) 61 and subtracting circuits 62 and 63, registers 65 and 66, and addition. Integrating circuits 69 and 70 including circuits 67 and 68 are provided. The comb filter 54 calculates a moving average of the bit string data input from the ΔΣ modulation circuit 52, and sequentially outputs the calculation result data to a FIR (Finite Impulse Response) filter 55.

As shown in FIG. 5, the FIR filter 55
Displays the data input from the comb filter 54 in the RAM 7
Sequentially stored in 1. The data stored in the RAM 71 is added by the adder circuit 74 via the registers 72 and 73 and stored in the register 75. The multiplication circuit 76 inputs the data from the register 75, multiplies the data by a preset coefficient stored in a coefficient ROM (Read Only Memory) 77, and sequentially stores the data in the register 78. The data stored in the register 78 is cumulatively added by a predetermined number by the adder circuit 79 and the register 80, and is output as digital data Dout.

Further, the FIR filter 55 is provided with an offset cancel circuit 81. The offset cancel circuit 81 includes an offset storage register 82 and a selector 83. The offset storage register 82 is adapted to store digital data (offset data) corresponding to the offset by the ΔΣ modulation circuit 52.

The ΔΣ modulation circuit 52 is an analog circuit and is composed of a switched capacitor integration circuit, a comparator for quantization, and the like. Therefore, an offset voltage is generated in the operational amplifier forming the integrating circuit and the comparator itself for quantizing. Further, the capacitance of the capacitor forming the integrating circuit may deviate from the design value. Therefore, the modulator bit string data offset from the ΔΣ modulation circuit 52 is output due to the offset voltage of the operational amplifier or the displacement of the capacitance of the capacitor. As a result, the offset amount is added to the digital data output via the digital filter 53. Then, when the processing is performed based on the digital data, the offset causes the processing result to include an error. Therefore, a value corresponding to the result of processing the offset bit string data by the ΔΣ modulation circuit 52 by the digital filter 55 in advance is stored as offset data. Then, the offset is canceled by adding the stored offset data to the digital data Dout obtained by A / D converting the analog signal Ain.

This offset data is used in the A / D converter 5
This is done once when the driving power supply of No. 1 is turned on.
That is, the A / D converter 51 enters the offset cancel mode in which the offset amount of the ΔΣ modulation circuit 52 is calculated when the drive power source is turned on. In the offset cancel mode, the RAM 61 and the registers 65 and 66 of the comb filter 54 and the register 80 of the FIR filter 55.
Is reset (cleared). In addition, the ΔΣ modulation circuit 5
In the offset cancel mode, No. 2 switches its input terminal to input a reference voltage and outputs bit string data obtained by sampling the voltage.

The bit string data is subjected to decimation processing by the digital filter 53, and the processing result is output as digital data Dout. The output digital data Dout becomes offset data of the ΔΣ modulation circuit 52. This offset data is stored in the offset storage register 82 based on the latch signal LATCH.
Is stored. Then, the offset storage register 82
When the offset data is stored in the A / D converter 51,
Ends the offset cancel mode.

Thereafter, when A / D converting the analog signal Ain, the A / D converter 51 switches the selector 83 and outputs the offset data stored in the offset storage register 82 to the adding circuit 79. Adder circuit 79
Inputs the data stored in the register 78 based on the analog signal Ain, adds the data and the offset data, and stores the result in the register 80. Next, the A / D converter 51 switches the selector 83 to output the data stored in the register 80 to the addition circuit 79, and cumulatively adds the data stored in the register according to the next analog signal Ain. As a result, the A / D converter 51 uses the ΔΣ modulation circuit 5
The digital data Dout in which the offset due to 2 is canceled can be output.

[0012]

The A / D converter 51 is designed to reduce the quantization error by oversampling. The delta-sigma modulation circuit 52 composed of an analog circuit includes a comb filter 54 and FI.
The circuit scale is smaller than that of the R filter 55. Therefore, it is suitable for high integration as compared with a serial conversion type A / D converter, etc.
It is becoming more and more configured into chips. However, the offset cancel circuit 81 that cancels the offset of the ΔΣ modulation circuit 52 by the digital filter 53
Therefore, the problem is to reduce the circuit scale of the digital filter 53.

The present invention has been made to solve the above problems, and an object thereof is to provide an A / D converter capable of canceling an offset with a simple structure.

[0014]

According to a first aspect of the present invention, a continuously changing analog signal is quantized in accordance with a frequency higher than the frequency of the analog signal, and bit string data corresponding to the quantized value is quantized. A ΔΣ modulation circuit, a plurality of differentiating circuits for differentiating the bit string data output from the ΔΣ modulating circuit, and a plurality of integrating circuits for integrating the output of the differentiating circuit are connected in series. A provided with a first digital filter circuit and a second digital filter circuit for multiplying the data output from the first digital filter circuit by a predetermined filter coefficient and for sequentially cumulatively adding the multiplication results. In the / D converter, the integration circuit of the first digital filter circuit is obtained by inputting a predetermined reference voltage to the ΔΣ modulation circuit. Tsu preparative column data to corresponding to subject matter to store data output through said first digital filter circuit and a second digital filter circuit as the initial value of the integrating circuit.

According to a second aspect of the present invention, in the A / D converter according to the first aspect, the plurality of integrator circuits of the first digital filter circuit are provided in an integration circuit at a final stage and have an initial value of an integration process. The main point is to remember.

According to a third aspect of the present invention, in the A / D converter according to the second aspect, the integrator circuit that stores an initial value of the integration process stores the input data and stores the stored data. It is composed of a register that delays by a predetermined number of sampling times and outputs, and an adder that adds newly input data to the data output from the register and supplies the addition result to the register.

[0017]

Therefore, according to the invention described in claim 1, the first
A predetermined reference voltage is input to the ΔΣ modulation circuit, and the input reference voltage is output through the first and second digital filters to the first digital filter. It is stored as the initial value of the integration processing of the circuit.

According to the second aspect of the present invention, the initial value of the integration process is stored in the final integration circuit of the plurality of integration circuits provided in the first digital filter circuit. According to the third aspect of the invention, the integration circuit in which the initial value of the integration process is stored is composed of a register and an adder. Input data is stored in the register,
The stored data is output after being delayed by a predetermined sampling number. The adder adds the newly input data to the data output from the register, and the addition result is supplied to the register.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. As shown in FIG. 2, the A / D converter 1 includes an input circuit 2, a switching circuit 3, a ΔΣ modulation circuit 4,
A comb filter 5, a FIR filter 6, and a serial conversion circuit 7 are provided.

The input circuit 2 receives a system clock signal SCLK from the outside, generates clock signals φ ₁ and φ ₂ having a predetermined frequency based on the system clock signal SCLK, and outputs the clock signals φ ₁ and φ ₂ . Further, the input circuit 2 monitors the voltage of the driving power supply of the A / D converter supplied from the outside, and outputs the mode signal MODE for setting the offset cancel operation when the operating power supply is turned on. When the mode signal MODE is output from the input circuit 2, the A / D converter 1 performs the offset cancel operation. Then, when the offset cancel operation is completed, the input circuit 2
Stop MODE output. Mode signal MO from input circuit 2
When DE stops, the A / D converter 1 is adapted to perform a normal A / D conversion operation.

The driving power source is also supplied to the ΔΣ modulation circuit 4, both filters 5 and 6, and the serial conversion circuit 7.
Then, the ΔΣ modulation circuit 4, both filters 5, 6, and the serial conversion circuit 7 operate based on the supplied driving power source.

As shown in FIG. 3, the switching circuit 3 is an analog switch and has a continuously changing analog signal Ain.
You are typing. Further, the switching circuit 3 uses the reference voltage Vref.
(For example, an intermediate potential between the power supply potential and the ground potential) is input. The switching circuit 3 receives the mode signal from the input circuit 2.
MODE is input and the analog signal Ain or the reference voltage Vref is output to the ΔΣ modulation circuit 4 based on the mode signal MODE.

That is, the switching circuit 3 outputs the reference voltage Vref to the ΔΣ modulation circuit 4 during the offset cancel operation. Then, the switching circuit 3 does not perform the offset cancel operation, that is, outputs the analog signal Ain to the ΔΣ modulation circuit 4 in the normal A / D conversion operation.

As shown in FIG. 3, the primary ΔΣ modulation circuit 4
Is composed of an integration circuit 11, a comparison circuit 12, a delay circuit 13, a 1-bit D / A conversion circuit 14 and an addition circuit 15.

The ΔΣ modulation circuit 4 is connected to the switching circuit 3 and receives the analog signal Ain or the reference voltage Vref.
Further, the ΔΣ modulation circuit 4 receives the clock signals φ ₁ and φ ₂ from the input circuit 2. The ΔΣ modulation circuit 4 samples the analog signal Ain or the reference voltage Vref at a frequency that is an integral multiple (tens to hundreds of times) of the sampling frequency fs based on the clock signals φ ₁ and φ ₂ . In this embodiment, sampling is performed at a frequency 64fs, which is 64 times the sampling frequency fs.

That is, the integrating circuit 11 is connected via the adding circuit 15.
Input the clock signal φ ₁, Φ₂On the basis of
It integrates and outputs to the comparison circuit 12. The comparison circuit 12 is 1
Input quantizer with a reference potential Vref
And an integrating circuit based on the reference potential Vref
The signal input from 11 is quantized, and the quantized data is
Output. The delay circuit 13 uses the quantization from the comparison circuit 12.
Delay 1 sampling of data and 1-bit D / A conversion
Output to the adder circuit 15 as an analog signal via the circuit 14.
Force The adder circuit 15 uses the data input from the switching circuit 3.
Data, a 1-sample quantized and converted to an analog signal
Data before subtraction and the subtracted data
It is designed to output to 11.

The ΔΣ modulation circuit 4 quantizes the sampled data into 1 bit, and outputs the quantized data to the comb filter 5 at an interval of 64 fs as modulator bit string data.

As shown in FIG. 1, the comb filter 5 has R
An AM 21, subtractors 22 and 23, registers 24 and 25, and adders 26 and 27 are provided. The RAM 21 is connected to the output terminals of the subtracters 22 and 23,
The data output from each is sequentially input. Then, the RAM 21 delays the input data by a predetermined sampling number (16 samples in this embodiment) and sequentially outputs the delayed data to the subtractors 22 and 24. That is, each of the subtracters 22 and 23 has a value of 1
The data output 6 samples before is input, the newly input data is subtracted from the data, and a secondary differentiating circuit that outputs the subtraction result is configured to perform integration processing.

Registers 24 and 25 are added by adders 26 and 27.
, And the data output from the adders 26 and 27 are sequentially input. And register 2
Reference numerals 4 and 25 delay the input data by a predetermined sampling number (1 sample in this embodiment) and sequentially output the delayed data to the adders 26 and 27, respectively. That is, the adders 26 and 27 add a newly input data to the output data, respectively, and form a quadratic integration circuit that outputs the addition result, and perform integration processing.

The comb filter 5 receives the modulator bit string data from the ΔΣ modulation circuit 4. Furthermore, comb filter 5, the clock signals phi ₁ from the input circuit 2 receives the phi _2, the clock signal phi _1, adapted to operate on the basis of phi _2. Then, the comb filter 5 calculates the moving average of the input modulator bit string data by the secondary differentiating circuit and integrating circuit, and sequentially outputs the calculation result as multi-valued data of appropriate bits. The multi-valued data from the comb filter 5 is output at an interval of 64fs like the input modulator bit string data.

Further, the register 25 is provided with a ΔΣ modulation circuit 4
The offset data corresponding to the offset is stored as an initial value of the integration process. That is, the register 25 stores the offset amount according to the offset of the ΔΣ modulation circuit 4 detected in the offset cancel operation. When the offset cancel operation is completed and the normal A / D conversion operation is performed, the integrating circuit
The integration is started based on the stored offset amount.
Therefore, the data output from the comb filter 5 is ΔΣ
The data to which the offset of the modulation circuit 4 is added is output.

The RAM 21 and the register 24 are adapted to be reset (cleared) when the offset cancel operation and the normal A / D conversion operation are started. As shown in FIG. 1, the FIR filter 6 includes a RAM 3
1, registers 32 to 36, coefficient ROM 37, adder 3
8, 39 and a multiplier 40 are provided.

The FIR filter 6 is a stored program type filter and has a structure corresponding to the number of taps 2N-1. That is, the multi-valued data D (1) to D (2N-1) from the comb filter 5 are stored in the RAM 31. Multivalued data D (1) stored in RAM 31
-D (2N-1), multi-valued data D (1) -D (N) are sequentially stored in the register 32, and multi-valued data D (N) -D (2N-1) are stored in the register 33. Sequentially stored. The intermediate multi-valued data D (N) is stored in each register 3
2 and 33 are stored respectively. The adder 38 includes multi-valued data D (1) to D (1) to D sequentially stored in the registers 32 and 33.
(N), D (N) to D (2N-1) are read, data E (1) to E (N) obtained by adding the read data are generated, and stored in the register 34.

The coefficient ROM 37 has N coefficients K (1).
~ K (N) are stored. The multiplier 40 reads the data E (1) to E (N) stored in the register 34, and the coefficient K corresponding to the data E (1) to E (N).
(1) to K (N) are read from the coefficient ROM 37. The multiplier 40 then uses the data E (1) to E (N) and the coefficient K.
Data F (1) to F (F) multiplied by (1) to K (N)
(N) is generated and the resulting data F (1) to F (N)
Are sequentially stored in the register 35.

The adder 39 adds the data F (1) to F (N) stored in the register 35, and outputs the addition result, that is, the sum of the data F (1) to F (N) to the register 36. Store.

Data transfer from the RAM 31 to the registers 32 and 33, an adder 38, a multiplier 40, and an adder 39
Is calculated in synchronism with the system clock signal SCLK. That is, the FIR filter 6 is
The comb filter 5 is synchronized with the system clock signal SCLK.
20-bit multi-valued data is sequentially input, and the multi-valued data is multiplied by a preset coefficient and added. This calculation is repeated a number of times corresponding to the number of taps 2N-1, so-called convolution operation is performed, and only the signal component in the low frequency band is passed (LPF).

In general, the modulator bit string data output from the ΔΣ modulation circuit 4 includes a quantization error (quantization noise) when quantizing into 1 bit, and the quantization noise is the analog signal Ain. It exists in a frequency band much higher than the frequency. Therefore, quantization noise is removed by cutting the high frequency band with the LPF. Further, the FIR filter 6 sets the coefficient stored in the coefficient ROM 37 so that the gain of the pass frequency band becomes 1 time.

The calculation result stored in the register 36 is stored in the register 25 of the comb filter 5 as offset data according to the offset amount of the ΔΣ modulation circuit 4 during the offset cancel operation.

In general, when the product-sum operation is performed by the FIR filter 6, the multivalued data D (1)
Coefficients K (1) to K (2N−) corresponding to D (2N−1)
1) is set. Then, each multi-valued data D (1) to D
(2N-1) and its multivalued data D (1) to D (2N-).
The product (multiplication) of the coefficients K (1) to K (2N-1) corresponding to 1) is performed 2N times, and all the results are added.

By the way, the coefficients K (1) to K (2N-1)
Is symmetrical with respect to K (N), the multi-valued data D (1) and D (2N-1) are multiplied by the same value. Therefore, multi-valued data D (1), D (2
N−1) is added in advance, and the added data is multiplied by the coefficient K (1) to reduce the number of multiplications, and to reduce the number of coefficients K (1) to K (2N−1). Halved.

Next, the operation of the A / D converter 1 configured as described above will be described. When the drive power is turned on, A /
The D converter 1 first executes an offset cancel operation. That is, the input circuit 2 detects the turning on of the driving power and outputs the mode signal MODE. The switching circuit 3 inputs the mode signal, switches the analog switch, and changes the reference voltage Vref.
Is output to the ΔΣ modulation circuit 4. Com filter 5 is RA
The M21, the registers 24 and 25, and the FIR filter 6 are
The register 36 is reset (cleared).

Next, the input circuit 2 receives the system clock signal SCLK, generates clock signals φ ₁ and φ ₂ based on the system clock signal SCLK, and outputs them. ΔΣ
The modulation circuit 4 oversamples the input reference voltage Vref based on the clock signals φ ₁ and φ ₂ , and outputs to the comb filter 5 modulator bit string data in which the oversampled data is quantized into 1 bit. That is, the ΔΣ modulation circuit 4 oversamples its own offset amount and outputs the oversampled modulator bit string data.

The comb filter 5 calculates the moving average of the input modulator bit string data and outputs the calculated result to 2
The multi-valued data D of 0 bit is sequentially output. At this time, the multi-valued data D output from the comb filter 5 is Δ
It has a value corresponding to the offset amount of the Σ modulation circuit 4. However, the multi-valued data D still contains the quantization noise of the ΔΣ modulation circuit 4. Therefore, if this multi-valued data D is stored in the register 25 and used as offset data, the correct multi-valued data D will not be output due to the quantization noise of the ΔΣ modulation circuit 4.

The FIR filter 6 receives 2N multivalued data D (1) to 20N of the inputted 20-bit multivalued data D.
The product sum operation of D (2N) is performed, and the data G of the operation result
Are stored in the register 36. Since the gain of the pass frequency band of the FIR filter 6 is 1 in this data G,
It becomes a value according to the offset amount of the ΔΣ modulation circuit 4. The data G stored in the register 36 corresponds to the serial conversion circuit 7
Output to the register 25 of the comb filter 5
Output to

When the data G is output from the FIR filter 6 to the register 25, the input circuit 2 receives the latch signal LATCH.
Is output to the comb filter 5. Upon receiving the latch signal LATCH, the comb filter 5 stores the data of the opposite polarity of the data G from the FIR filter 6 in the register 25 as the initial value of the integrating circuit.

When the data having the reverse polarity of the data G is stored in the register 25, the input circuit 2 stops the output of the mode signal MODE. Then, the A / D converter 1 shifts from the offset cancel operation to the normal A / D conversion operation. After that,
In a normal A / D conversion operation, the register 25 that constitutes the final stage integration circuit of the comb filter 5 stores offset data having the opposite polarity of the offset amount of the ΔΣ modulation circuit 4. Then, the final stage integrating circuit is the register 2
The integral operation is performed from the initial value stored in 5. Therefore, the comb filter 5 outputs the multivalued data D in which the offset amount of the ΔΣ modulation circuit 4 is corrected (cancelled).

As described above, according to the A / D converter 1 of the present embodiment, in the offset cancel operation, the ΔΣ modulation circuit 4 receives the reference voltage Vref and inputs the reference voltage Vre.
Outputs the modulator bit string data obtained by oversampling f. The digital decimation filter including the comb filter 5 and the FIR filter 6 inputs the modulator bit string data and generates data G in which the frequency of the bit string data is reduced.

The data having the opposite polarity of the generated data G is stored in the register 25 constituting the final stage integrating circuit of the comb filter 5 as the initial value of the integrating circuit. In the normal A / D conversion operation, the integration circuit at the final stage of the comb filter 5 performs the integration operation from the initial value stored in the register 25. Therefore, the data output from the comb filter 5, that is, the integration result output from the adding circuit 27 is added by the offset data and output.
As a result, the offset amount of the ΔΣ modulation circuit 4 is corrected and output according to the initial value of the integration circuit at the final stage, so that the conventional offset cancel circuit 80 is unnecessary, and the offset of the ΔΣ modulation circuit 4 is canceled with a simple configuration. can do.

Further, since the offset cancel circuit 80 of the conventional A / D converter 51 becomes unnecessary, the circuit scale of the A / D converter 1 can be reduced, and the same circuit as other circuits such as a CPU can be provided. It becomes easy to integrate into.

The present invention may be carried out as follows in addition to the above embodiment. 1) In the above embodiment, the offset cancel operation is automatically performed when the drive power of the A / D converter 1 is turned on, but the offset cancel operation may be performed other than when the drive power is turned on. For example, the input circuit 2 inputs a signal for instructing an offset cancel operation from the outside, and outputs a mode signal MODE indicating the offset cancel operation based on the input signal. The switching circuit 3, the ΔΣ modulation circuit 4, and the filters 5 and 6 may perform the offset cancel operation based on the mode signal MODE.

2) In the above embodiment, the embodiment is embodied as an A / D converter using the second-order comb filter 5. However, according to the order of the ΔΣ modulation circuit 4, an A / D converter using a third-order or higher-order comb filter is used.
It may be embodied in a D converter and implemented.

Further, in the above embodiment, the embodiment is embodied as an A / D converter using the ΔΣ modulation circuit 4, but it is also embodied as an A / D converter using the Δ modulation circuit and the ΔΣ modulation circuit. May be.

3) In the above embodiment, the A / D converter provided with one ΔΣ modulation circuit 4 is embodied, but two or more ΔΣ modulation circuits and the respective ΔΣ modulation circuits are inputted. A switching circuit for switching the modulator bit string data by time division and outputting it to the comb filter 5 may be provided.

The RAM 21, the registers 24, 25 of the comb filter 5, the RAM 31, and the registers 32 to 36 of the FIR filter 6 are provided in a plural number according to the number of ΔΣ modulation circuits so that they can be switched simultaneously with the analog input signal. There is a need.

4) In the above embodiment, the frequencies of the clock signals φ ₁ and φ ₂ for sampling the analog signal Ain are set to 64 times the sampling frequency fs (64 fs), but 16, 32, 128 times, etc. The frequency may be set to any integral multiple.

5) In the above embodiment, the switching circuit 3 is provided,
Although the reference voltage Vref is supplied to the ΔΣ modulation circuit 4 when the offset cancel operation is performed based on the mode signal MODE, the reference voltage Vre is changed to the analog signal Ain during the offset cancel operation without providing the switching circuit 3.
The offset cancellation of the ΔΣ modulation circuit 4 may be performed by supplying f. With this configuration, the circuit scale of the A / D converter 1 can be further reduced.

Although the respective embodiments of the present invention have been described above, technical ideas other than the claims which can be understood from the respective embodiments will be described below together with their effects. A) A / D according to any one of claims 1 to 3.
The converter is provided with an input circuit 2 that monitors a driving power source supplied from the outside and outputs a mode signal MODE based on the driving power source. The ΔΣ modulation circuit 4 and the first and second digital filter circuits (5 , 6) is the mode signal
An A / D converter that performs an offset cancel operation based on MODE. With this configuration, offset cancellation can be easily performed.

B) A according to claims 1 to 3 or b) above
In the A / D converter, the data output from the second digital filter circuit is input, the A / D converter includes a serial conversion circuit 7 that serially converts the data and outputs the data to the outside.
D converter. With this configuration, the number of output terminals can be reduced and the package can be downsized.

C) In the A / D converter according to any one of claims 1 to 3 or above a) or b), a switching circuit 3 for switching and outputting the analog signal Ain and the reference voltage Vref based on the mode signal MODE. A / D converter provided. With this configuration, the offset data according to the offset amount of the ΔΣ modulation circuit 4 can be easily set.

[0060]

As described above in detail, according to the present invention, it is possible to cancel the offset with a simple structure.
A / D converter can be provided.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a digital filter according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram of an A / D converter according to an embodiment.

FIG. 3 is a circuit diagram of a ΔΣ modulation circuit according to an embodiment.

FIG. 4 is a block circuit diagram of a conventional oversample A / D converter.

FIG. 5 is a block circuit diagram of a conventional FIR filter.

FIG. 6 is a block circuit diagram of a conventional comb filter.

[Explanation of symbols]

1 A / D converter 2 Input circuit 3 Switching circuit 4 ΔΣ modulation circuit 5 Comb filter as first digital filter circuit 6 FIR filter as second digital filter circuit 25 Register 27 Adder Ain Analog signal MODE mode signal Vref Reference voltage

Claims (3)

[Claims] 1. A continuously changing analog signal (Ain)
Is quantized according to a frequency higher than the frequency of the analog signal (Ain), and bit string data corresponding to the quantized value is generated, and a ΔΣ modulation circuit (4) is output from the ΔΣ modulation circuit (4). A plurality of differentiating circuits for differentiating the bit string data and a first digital filter circuit (5) in which a plurality of integrating circuits for integrating the outputs of the differentiating circuits are connected in series; An A / D converter comprising a second digital filter circuit (6) for multiplying data output from the filter circuit (5) by a predetermined filter coefficient, and for sequentially cumulatively adding the multiplication results, The integration circuit of the first digital filter circuit (5) corresponds to bit string data obtained by inputting a predetermined reference voltage (Vref) to the ΔΣ modulation circuit (4). An A / D converter characterized by storing the data output through the first digital filter circuit (5) and the second digital filter circuit (6) as an initial value of an integrating circuit. 2. The A / D converter according to claim 1, wherein the plurality of integration circuits of the first digital filter circuit (5) store an initial value of integration processing in an integration circuit at a final stage. An A / D converter characterized by: 3. The A / D converter according to claim 2, wherein the integrator circuit that stores the initial value of the integration process stores the input data and delays the stored data by a predetermined sampling number. Register to output (25)
And an adder (27) for adding the newly input data to the data output from the register (25) and supplying the addition result to the register.
/ D converter.