JPH04127638A - Fsk demodulation circuit - Google Patents

Abstract

PURPOSE:To improve considerably code distortion by providing a zero cross point detection circuit, a counter, a decoder, 1st and 2nd pulse generating circuit and a gate circuit to the demodulation circuit. CONSTITUTION:The demodulation circuit consists of a zero cross point detection circuit 2, a counter 3, a decoder 4, 1st pulse generating circuit 5, a 2nd pulse generating circuit 6 and an OR circuit 7. That is, the zero cross point detection circuit 2 consists of a comparator 10 and a differentiating circuit 11, the 1st pulse generating circuit 5 consists of an RS latch circuit 17 and the 2nd pulse generating circuit 6 consists of a counter circuit 19 and an RS latch circuit 18 respectively. In this case, it is possible to demodulate and reproduce a data having a same pulse width (data width) as that of an original binary digital signal. Thus, code distortion due to a reproduced data pulse width error is considerably improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FSK demodulation circuit, and more particularly to an FSX demodulation circuit in which code distortion is significantly improved in a digital counting method.

[Conventional technology]

One of the common methods used for digital data communication in modems, acoustic duplexers, etc. is the so-called frequency shift keying method, which transmits data by assigning "0" to a high frequency and "1" to a low frequency in a data signal. There is a method (hereinafter referred to as FSX).

The demodulation circuit of this FSK method includes a frequency discrimination method,
Some of them are based on analog circuits such as the PLL system, but they have drawbacks such as a large circuit scale, a large number of parts, and many adjustment points, making it difficult to reduce the size and cost.

On the other hand, there is a digital counting method that detects the zero crossing point of the FSX signal, measures this interval with a counter, and demodulates digital data based on the magnitude of the counter value. The demodulation circuit using this digital counting method is mostly a digital circuit, so
It has the advantage of being able to be miniaturized and have low power consumption due to its integrated circuit structure.6 Next, a demodulation circuit using a digital counting method will be explained.

FIG. 5 is a block diagram of an example of an FSK demodulation circuit using a general digital counting method, and FIG. 6 is a timing chart of waveforms at each point in FIG.

FIG. 6(a) shows the original binary digital signal, which is FSX-modulated on the transmitting side to produce the FSX signal shown in FIG. 6(b).
It becomes an SX modulated signal and is transmitted through the line.

In FIG. 5, the FSX modulation signal (FIG. 6(b)) is transmitted to the comparator 10. The signal is input to the input terminal 1 of the zero-cross point detection circuit 2 composed of the differentiating circuit 11. This input FSX modulation signal is converted into a digital binary signal (FIG. 6(C)) by the comparator 10, and this digital binary signal is further differentiated by the differentiating circuit 11, and the sixth
The signal is converted into a zero-cross pulse signal as shown in FIG. 3(d) and input to the counter 3. The counter 3 counts clock signals at intervals of the input zero-cross pulse signal, and inputs the count value result to the decoder 4. The decoder 4 determines the frequency of the original binary signal based on the count value of the counter 3, and outputs the result as a pulse. That is, when a pulse count value C1 is detected during a period of pulse width T1 of a low-frequency signal component corresponding to 1 part of the original binary signal, the pulse count value C1 shown in FIG. 6 from the terminal 15 is detected.
When the pulse shown in e) is output and the pulse count value C2 of the pulse width T2 period of the high frequency signal component corresponding to the original binary signal "0P" is detected, the pulse shown in Fig. 6 (f) is output from the terminal 16. ) is set so that the pulse shown by is output.

These output pulses are input to the set terminal S and reset terminal R of the RS latch circuit 17, respectively, and as a result, the pulses shown in FIG. 6(e) are set (“1” level output), and the pulses shown in FIG. 6(f) are set (“1” level output). is reset (“O” level output) with the pulse of
The demodulated signal (Fig. 6(b)) obtained by demodulating the K signal (Fig. 6(b))
g)) is output.

As explained above, the digital counting method detects the frequency components of the FSX modulated signal and demodulates the original binary signal by determining the zero-crossing points of the input FSX modulated signal and counting the clock signals at the zero-crossing intervals. I can do it. According to this method, counters, decoders, RS latch circuits, etc. are relatively easy to integrate into ICs using CMO3 or the like because they process digital signals, and furthermore, there are advantages such as no adjustment is required.

[Problem to be solved by the invention]

FSK of the conventional digital counting method mentioned above
In the demodulation circuit, there are factors that worsen code distortion due to the method itself. In other words, in the digital counting method, the time between the zero crossing points of the original binary digital signal is measured, and the "0" and 1" levels of the original binary digital signal are determined based on the measured value results. A delay time occurs in the reproduced/demodulated signal at the change point of the digital signal, and as a result, the pulse width of the reproduced/demodulated signal does not match the original signal.
) and the demodulated signal in Figure 6(g), we find that at the rise to the 1'° level, T
A delay time of I occurs, and a delay time of T2 occurs at the falling change point from the "1'° level to the "0" level.

As a result, the °'1'' level period A1 of the demodulated signal is
For the P1'' level period A of the value digital signal, it changes as shown in the following equation.

A1=A-T1+T2...
(1) Also, the "o" level period B1 of the demodulated signal changes as shown in the following equation with respect to the "0" level period B of the original binary digital signal.

B, = B + T1 - T2 ... (2) In other words, the data signal width has an error of (T2 - TI > (TIT2)) with respect to the original binary digital signal, and this is the cause of data error (sign Distortion), which makes it difficult to reproduce accurate data.

SUMMARY OF THE INVENTION An object of the present invention is to provide an FSK demodulation circuit which eliminates such drawbacks and reduces causes of code distortion by compensating the data width of a demodulated data signal.

[Means to solve the problem]

The configuration of the FSX demodulation circuit according to the present invention uses frequency shift modulation (FS
K) A zero-crossing point detection circuit that receives a signal as input and detects a zero-crossing point, a counter that counts clock signals during a period between two consecutive zero-crossing points from the output of this zero-crossing point detection circuit, and a first counter of this counter. a decoder that outputs a first pulse in response to a count value output and a second pulse in response to a second count value output; and a decoder that is set by the first pulse and reset by the second pulse. a first pulse generating circuit; a second pulse generating circuit that outputs a pulse having a width corresponding to the first count value using the first pulse as a trigger; an output of the first pulse generating circuit; It is characterized by comprising a gate circuit that performs a logical sum with the output of the second pulse generating circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an FSK demodulation circuit according to an embodiment of the present invention.
, counter 3, decoder 4, first pulse generation circuit 5,
It is composed of a second pulse generation circuit 6 and an OR circuit 7.

FIG. 2 is a block diagram showing a specific example of FIG. 1. In the figure, a comparator 10 and a differentiating circuit 11 constitute a zero cross point detection circuit 2, an RS latch circuit 17 constitutes a first pulse generation circuit 5, and a counter circuit 19 and an RS latch circuit 18 constitute a second pulse generation circuit. 6 respectively.

First output terminal 15 and second output terminal 16 of decoder 4
The signal outputted from is the same as the conventional example. That is, the FSK modulated signal shown in FIG. 6(b) is input to the input terminal 1 of the zero cross point detection circuit 2, converted by the comparator 10 into the digital binary signal shown in FIG. 6(c), and differentiated by the differentiator 11. is converted into a zero-cross pulse signal shown in FIG. 6(d), and is input to the counter 3. The counter 3 counts the clock signals at intervals of the input zero-cross pulse signal, and inputs the count value result to the decoder 4. The decoder 4 determines the frequency of the original binary signal based on the magnitude of the count value from the counter 3, and outputs the result as a pulse. That is, when the pulse count value C1 of the pulse width T1 period of the low frequency signal component corresponding to "1" of the original binary signal is detected, the pulse shown in FIG. 6(e) is output from the terminal 15. When the pulse count value C2 of the pulse width T2 period of the high frequency signal component corresponding to "0" of the original binary signal is detected, the pulse 2 shown in FIG. 6(f) is output from the terminal 16. be done.

The pulse shown in FIG. 6(f) is input to the set terminal S of the RS latch circuit 17, and is also input to the set terminal S of the RS latch circuit 18 and one counter circuit.
The pulse f) is input to the reset terminal R of the RS latch circuit 17.

The RS latch circuit 17 is similar to the conventional example as shown in FIG. 6(e).
It is set (“1” level output) with the pulse of Figure 6 (
It is reset ("0" level output) by the pulse f), and as a result, the pulse shown in FIG. 6(g) is output from the output terminal 20 of the RS latch circuit 17. As mentioned above, this output signal has a delay time of T1 at the rise to the "1" level with respect to the original binary digital signal, and a delay time of T2 at the falling change point from the 1' level to the °'0' level. A delay time occurs, and as a result, the 1" level period A of the demodulated signal in FIG.
The "0" level period B1 of the demodulated signal changes with respect to the level period A (A-Tl+T2), and the "0" level period B1 of the original binary digital signal changes (B+7l-T2) with respect to the original binary digital signal.
The value does not match the digital signal.

Next, explanation will be given using the timing chart shown in FIG. 3(a) corresponds to the input waveform in FIG. 6(a), and FIG. 3(b) corresponds to the output waveform in FIG. 6(g).

In the second pulse generating circuit 6, the pulse shown in FIG. 3(C), which is the same as that shown in FIG. 6(e), is input from the decoder 4 to the counter circuit 19, and this pulse is used as a trigger to count the clock signal. When the count value reaches a preset time T11, a reset pulse (Fig. 3(d)
) is output and supplied to the reset terminal R of the RS latch circuit 18. The RS latch circuit 18 is set (outputs "1" level) by the pulse shown in FIG. 3(C) input to the set terminal S, and reset (outputs "0" level) by the reset pulse (FIG. 3(d)) ), and as a result, a compensation pulse (FIG. 3(e)) is applied from the output terminal 21 of the RS latch circuit 18.

The OR circuit 7 receives the pulse signal from the RS latch circuit 17 (FIG. 3(b)) and the compensation pulse from the RS latch circuit 18 (FIG. 3(e)), and calculates the logic of both pulse signals. The sum is obtained, and the final demodulated signal (Fig. 3 (f)) is output from the output terminal 8. The timing chart of each of the above signals is as shown in Fig. 3. If the pulse width of the demodulated signal is A, then A+-(A-'rl+T1
1). Also, 0'° level darkness B, = (
B−Tl 1+71 ). Here, by setting the count setting value T1·1 of the counter circuit 19 to T11, A, = A, B, = B is obtained, and the demodulated signal has the same pulse width and data width as the original binary digital signal. can be played. Note that the output signal in FIG. 3(f) corresponds to FIG. 6(h) in FIG. 6.

FIG. 4 is a block diagram showing another specific example of FIG. 1.

In this figure, the function of the counter circuit 19 constituting the second pulse generating circuit 6 of FIG. 2 is realized by a delay circuit 22. That is, by inputting the pulse shown in FIG. 3(c) from the decoder 4 to the delay circuit 22 and setting the delay value of the delay circuit 22 to be equal to Tll, the third The reset pulse shown in Figure (d) can be obtained, and by inputting this pulse to the reset terminal R of the RS latch circuit 18 as a reset pulse,
Similar to the first specific example, it is possible to reproduce a demodulated signal having the same pulse width as the original binary digital signal.

〔Effect of the invention〕

As explained above, according to the present invention, the digital counting type FSK demodulation circuit can demodulate and reproduce the same pulse width (data width) as the original binary digital signal, and the conventional demodulation circuit can demodulate and reproduce the same pulse width (data width) as the original binary digital signal. The code distortion caused by the reproduced data pulse width error can be significantly improved.
Therefore, it is possible to significantly reduce data errors during reproduction, and it is also easy to integrate into an integrated circuit, eliminating the need for adjustment, making it possible to achieve smaller size and lower power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a timing diagram explaining the operation of FIG. 2, FIG. 4 is a block diagram showing another specific example of FIG. 1, and FIG. 5 is a conventional FSK demodulation circuit. FIG. 6, which is a block diagram of an example, is a timing diagram explaining the operation of FIG. 5. 1... Zero cross point detection circuit input terminal, 2...
・Zero cross point detection circuit, 3... Counter, 4
... Decoder, 5... First pulse generation circuit, 6.
...Second pulse generating circuit, 7...OR circuit, 8.
...Demodulated signal output terminal, 10...Comparator, 11
...Differential circuit, 15.16...Decoder output terminal,
17゜18...RS latch circuit, 19...Counter circuit, 20.21...RS latch circuit output terminal, 22
...Delay circuit.

Claims (1)

[Claims] A zero cross point detection circuit that receives a frequency shift keying (FSK) signal whose frequency changes in accordance with a binary digital signal and detects zero cross points, and a period between two successive zero cross points from the output of this zero cross point detection circuit. a counter that counts clock signals; a decoder that outputs a first pulse in response to a first count value output of the counter; and a second pulse in response to a second count value output of the counter; a first pulse generating circuit that is set by the first pulse and reset by the second pulse; and a second pulse generating circuit that outputs a pulse having a width corresponding to the first count value using the first pulse as a trigger. An FS characterized by comprising a pulse generation circuit and a gate circuit that outputs a logical sum of the output of the first pulse generation circuit and the output of the second pulse generation circuit.
K demodulation circuit.