JPS62147830A - Timing recovery system - Google Patents

Abstract

PURPOSE:To stabilize the phase pull-in operation by deciding the amplitude of in-phase and orthogonal components of the phase while utilizing in-phase/ orthogonal demodulation signals deciding the amplitude valve of in-phase orthogonal components to set the timing initial phase. CONSTITUTION:The in-phase/orthogonal demodulation signals inputted to an in-phase/orthogonal demodulation signal level discriminating circuit 24 is subject to level decision and when any of them exceeds a prescribed value, the output is fed to an AND circuit 25, where the output of the counter 23 and the output of the circuit 24 are decided to activate a switch 26. A control circuit 27 starts its operation when the switch 26 is turned on, and the time difference between the operating start point and the point of time when the output of a period decision circuit 21 is inputted is calculated to correct the phase at the start of a recovery timing clock. Further, the time when the output of the circuit 21 is inputted and a recovery symbol timing are compared and if the time is deviated, the deviated time difference is replaced into the lead/lag of the phase, the frequency divider of the control circuit 27 is switched to generate a recovery symbol timing, a recovery bit timing and a sample clock.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timing regeneration method for a data transmission modem used for mobile communication such as a car telephone.

(Prior art) Conventionally, many of these types of devices have been constructed with analog circuits, and even when using di-notal circuits or di-notal signal processing technology, the analog circuits have generally been replaced. be. Figure 4 shows a conventional timing recovery circuit (
Oki Electric Research and Development, Vol. 43. A2, March 1972, and Japanese Unexamined Patent Publication No. 58-123262).

FIG. 4(,) shows a timing extraction block, and FIG. 4(b) shows a timing extraction block. Figure 4 (,)
Its function is to pass the simple periodic components contained in the in-phase/quadrature demodulated signal through bandpass filters 1a and Ib, which extract the simple periodic components. This is further passed through full wave rectifiers 2a*2b to create a second harmonic component. After the second harmonic components are added by an adder 3, they are passed through a bandpass filter 4 that passes the second harmonic components to extract a timing signal.

Slice this at zero level and at a high level above a certain level. The signals TIM-0 and TIM-H determined by the zero level determination circuit 6 and the high level determination circuit 5 are created by a slicer,
The TTM-00 phase when TIM-H is obtained is used as a reliable timing phase in the timing recovery circuit of FIG. 4(b).

The timing recovery circuit is TIM- with flip-flop 2.
Extract the TIM-0 manual conversion point when there is an input of H. The phase shifter 8 is composed of a monostable multi-vibrator,
Used to set the initial pull-in phase. The rising point of the output of the phase shifter 8 is differentiated by a differentiating circuit 9 using a clock. The flip roller flO is set by this differential pulse, and reset at the rising edge of the reproduction timing of the counter 15, and the phase difference is output.The counter 11 counts this phase difference, and if the phase difference is large, the gate 13 is opened to pass the differential output, and if the differential output is small, f-gate 13 is closed. The output of the differentiating circuit 9 and the APC output are compared in phase lead and lag in the control circuit 14, and the clock A? of the frequency dividing circuit in the control circuit 14 is compared. Advance/delay control is performed by inserting and removing the pulses, and the APc output phase is controlled to follow the differential circuit output phase.

(Problem to be Solved by the Invention) However, in the timing regeneration circuit with the above configuration, only the level of the timing regeneration signal is used when used in a transmission line where many errors occur in mobile communications such as car telephones. Since the flip-flops are operated by the input signal, the initial phase pull-in point malfunctions due to noise, and the phase pull-in point is not the best point for the in-phase/quadrature demodulated signal.

This invention eliminates the above-mentioned disadvantages that the initial phase pull-in point becomes unstable due to noise and the disadvantage that the phase pull-in point becomes a point where there is a bad error between the phase judgment error value of the in-phase/quadrature demodulated signal, and The purpose of this is to obtain a timing reproduction signal that stabilizes phase pull-in and reduces phase determination errors of in-phase and quadrature demodulated signals.

(Means for Solving the Problems) This invention is designed to stably generate initial phase and timing reproduction signals in data transmission modems used in transmission lines where many errors occur in mobile communications such as car telephones. level determination means for determining the level of the timing extraction signal (referring to reproduction syndel timing unless otherwise specified); and means for determining the cycle of the timing extraction signal;
A means is provided for determining the levels of the in-phase demodulated signal and the orthogonal demodulated signal and to match the initial phases of the timing signals.

(Function) In the present invention, by these means, it is detected that the period in which the timing extraction signal occurs continues for a certain period at a predetermined symbol rate, it is detected that the level of the demodulated signal is high to a certain extent, and these two The timing initial phase is set based on the conditions. Therefore, the initial pull-in phase is less likely to become unstable due to noise or the like.

(Embodiment) Figure i1 is a circuit diagram showing an embodiment of the present invention, in which the in-phase demodulated signal and quadrature demodulated signal are input to the input terminals IA and 2B by a bandpass filter (BPF) for every 9.6 kHz sample.
1a and Ib. Further, the demodulated signal enters the in-phase/quadrature demodulated signal level determination circuit 24. The in-phase and quadrature demodulated signals input to the input terminals Ik and 1B are passed through a bandpass filter 1a h 1b to a full-wave rectifier (ABS).
2a #2b, the in-phase and quadrature components are added by an adder 3 and input to a bandpass filter 4, and the output of the bandpass filter 4 is input to a high level determination circuit 20 and a period determination circuit 2. The output of the high level judgment circuit 20 operates the gate 22. One of the outputs of the period judgment circuit 21 is sent to the counter 23 and the control circuit 27 through the dart 22. The other output is used for high level judgment. The output of the counter 23 enters the AND circuit (AND) 25, and the AND output with the output of the in-phase/quadrature demodulation signal level determination circuit 24 is combined with the output of the switch (SW) 261/C input n1 switch 26. It is integrated into the control circuit 27.

First, the in-phase and quadrature demodulated signals that entered the input terminals 7A and IB are in-phase by the bandpass filters 1a and Ib.

Extract the symbol period component included in the orthogonal demodulated signal.

This symbol periodic component is converted into a full-wave rectifier 2a.

2b for full wave rectification, an adder 3 for addition, and a band filter 4 for extracting a timing signal.

The extracted timing extraction signal is sent to the high level determination circuit 2.
0 is input to the period determination circuit 2. The high level determination circuit 20 determines the level of the timing extraction signal and determines the level of the timing extraction signal.
22 is operated. Further, the high level determination circuit 20 is reset by the output of the period determination circuit 21. The period determination circuit 21 determines the falling edge of the timing extraction signal,
Count the period until the next falling edge. The result of comparing the determined period with the symbol rate is inputted to the counter 23 and the control circuit 27 through the r-gate 22.

In addition, Goo 822 of the timing period determination and comparison results
When the passage is completed, the high level determination circuit 20 is reset. In the counter 23, when the comparison result output of the period determination circuit 21 indicates that it is equal to the symbol rate, the counter 23 outputs a value of 1.
When the value exceeds a certain value, an operation output is sent to the AND circuit 25, and the counter 23 stops adding and holds the output.

Each time a value indicating that the counter 23 is not equal to the symbol rate is inputted before reaching a constant value,
Reset the counter 23. The level of the in-phase/quadrature demodulated signal input to the in-phase/quadrature demodulated signal level determination circuit 24 is determined, and if either one exceeds a certain value, the output is passed to the AND circuit 25.

The AND circuit 25 determines the output of the counter 23 and the output of the in-phase orthogonal demodulated signal level determination circuit 24, and
Operate 6.

The timing period output of the period determination circuit 21 is input to the control circuit 27, and the time at which this input is performed is at the point at which the timing extraction signal falls, and if the gate 22 is not open at this time, it will not be input.

The control circuit 27 starts operating when the switch 26 is turned on, and calculates the time difference between this operating point and the output of the period determination circuit 21, and corrects the phase at the start of the reproduction timing clock. .

Thereafter, the time when the output of the period determination circuit 21 was input is compared with the playback simple timing, and if the time is different,
The control circuit 2 replaces this n time difference with phase lead/lag.
By switching the 70 frequency divider, reproduced symbol timing, reproduced bit timing, and sample clock are generated. FIG. 2 (,) shows waveforms for explaining the operation of the in-phase/quadrature demodulated signal level determination circuit.

Points A, B, and C in FIG. 2 indicate the deviation in the start time of the control circuit 27, and FIG. 2(b) shows the amplitudes at points A, B, and C in terms of phase. From this, the error with the phase reference value is the smallest at point C, and the initial pull-in time is short. This amplitude value is such that the modem training is initially in two phases of 0-π, so the amplitude value at a phase angle of 45° is the best value in the worst case at the time of initial phase acquisition. In addition, Fig. 2(b)
, (Xr, yr) indicates the reference phase point, and EYC
,! : EXC indicates the difference between point C and the reference phase point.

FIG. 3 is a flowchart of this initial set timing regeneration circuit. Assuming that the timing extraction signal (hereinafter referred to as BOUT) of the output of the bandpass filter 4 in FIG.
The level of OUT is determined by the high level determination circuit 20, and LEV
Set ELSW. Next, in step (2), it is determined whether BOUT falls, and in step (2), the cycle of BOUT is checked and set to Bcount. Furthermore, counter 2
3 and if the counter 23 is not on, the color/
At step 23, Bcount and LEVELSW are determined and data is set. Next, judge LEVELSW as 1-
If LEVELSW is 1, the symbol rate and Be
Compare oun t and find the lead or lag in phase. When the above operations are completed, LEVELSW is reset to 0. In step (2), the switch 26 is determined, and when the switch 26 is turned on, the control circuit 27 starts operating, and in step (2) the frequency divider is operated. When the switch 26 is off, the amplitude of the in-phase/quadrature demodulated signal is determined in step ■, and the amplitude is set to a constant value (
LEVEL2), the counter 23 is further determined, and if the counter 23 is on, the switch 26 is turned on and control of the frequency divider in step (2) is started. This flowchart can be realized by this first dinotal signal processing.

(Effects of the Invention) Therefore, according to the present invention, the timing initial phase is set by determining the amplitude values of the in-phase and quadrature components of the phase using the in-phase and quadrature demodulated signals. In addition, when setting the timing, the symbol rate and the timing extraction signal are compared in order to prevent malfunctions due to noise, etc., and the initial phase is stabilized. Therefore, when transmitting data using mobile communication such as a car phone, it is possible to create a stable timing recovery circuit for a data modem without causing the initial pull-in phase to become unstable even due to noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. FIG. 3 is a flowchart of this initial set timing regeneration circuit, FIG. 4(,) shows a conventional timing extraction block, and FIG. 4(b) shows a conventional timing extraction block. 1...BPF, 2...Full wave rectifier circuit, 3...Addition circuit, 4...BPF, 2c+...High level judgment circuit, 21...Period judgment circuit, 22...Dirt , 23・
... Counter, 24... In-phase, orthogonal demodulation signal level determination circuit, 25... AND circuit, 26... Switch,
27...Control circuit. Daiminpu"j1 main item shiflow child dart figure 3

Claims (1)

[Claims] Means for determining the level of the timing extraction signal, means for determining the period of the timing extraction signal, determination of the timing extraction signal level during initial operation, and comparison of the period of the timing extraction signal and the symbol rate. What is claimed is: 1. A timing regeneration method comprising: means for performing the following steps; and means for determining demodulation levels of in-phase and quadrature signals, and setting an initial phase of timing.