JPH0547011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timing recovery circuit for a data transmission modem used in mobile communication such as a car telephone.

(Prior art) Conventionally, many of these types of devices have been constructed with analog circuits, and even when digital circuits or digital signal processing technology is used, the analog circuits are generally replaced. . Figure 4 shows a conventional timing regeneration circuit (Oki Electric R&D,
Vol.43.No.2, March 1972, and JP-A-1982-
123262)). Figure 4a shows the timing extraction block diagram, and Figure 4b shows the timing extraction block diagram.
Shows APC block. The function of FIG.
Extract the periodic component twice the symbol period. This is further passed through full-wave rectifiers 2a and 2b to create a second harmonic component. After the second harmonic components are added by an adder 3, they are passed through a bandpass filter 4 that passes the second harmonic components to extract a timing signal. This is sliced into zero level and high level above a certain level. The signals TIM-O and TIM-H determined by the zero level determination circuit 6 and the high level determination circuit 5 are created using a slicer,
The phase of TIM-O when TIM-H is obtained is used as a reliable timing phase in the timing APC circuit of FIG. 4b.

The timing APC circuit is flip-flop 7.
Extract the TIM-O input conversion point when there is a TIM-H input. The phase shifter 8 is composed of a monostable multi-vibrator and is used to set the initial pull-in phase. The rising point of the output of the phase shifter 8 is differentiated by a differentiating circuit 9 using a clock. The flip-flop 10 is set by this differential pulse, and reset at the rising edge of the reproduction timing of the counter 15, and the phase difference is output.The counter 11 counts this phase difference, and if the phase difference is large, opens the gate 13. The differential output is passed through, and if the differential output is small, the gate 13 is closed. The output of the differentiating circuit 9 and the APC output are compared in terms of phase lead and lag in the control circuit 14, and the control circuit 14 performs phase advance/delay control by inserting and removing clock pulses of the frequency dividing circuit.
The APC output phase is controlled to follow the differential circuit output phase.

(Problem to be solved by the invention) However, in the timing recovery circuit with the above configuration,
For use in transmission lines where many errors occur in mobile communications such as car phones, flip-flops are operated using only the level of the timing recovery signal, so the initial phase pull-in point may malfunction due to noise, causing the phase The drawback was that the pull-in point was unstable.

In addition, initial phase pull-in may be performed at the point when the level of the in-phase/quadrature demodulated signal is not stable (at the point when the output of the automatic gain control circuit in the previous stage is not stable). It had the drawback of being unstable.

Therefore, an object of the present invention is to reduce the influence of noise on the initial phase pull-in point so that it can be carried out stably at the zero-crossing point.

(Means for Solving the Problems) The present invention provides a first means for creating a timing extraction signal by extracting a symbol period component using an in-phase demodulated signal and an orthogonal demodulated signal as input.
It has a, 1b, 2a, 2b, 3, and 4.

and second means 20 for detecting that the level of the timing extraction signal exceeds a predetermined threshold;
The third signal detects the cycle length from the zero-crossing point of the falling edge of the timing extraction signal to the zero-crossing point of the next falling edge, and outputs it at the zero-crossing point of the falling edge.
It has means 21.

Also, based on the outputs of the second means and the third means,
fourth means 22, 23 for outputting a first start signal when the period length of the timing extraction signal is equal to the symbol period length and the level of the timing extraction signal exceeds a predetermined threshold value for a predetermined number of periods continuously;
and has.

Further, it has a fifth means 24 for determining the levels of the in-phase demodulated signal and the orthogonal demodulated signal, and outputs a second start signal when the level of either one exceeds a predetermined threshold.

Further, sixth means 25 and 26 for outputting a zero cross point of the fall of the timing extraction signal in the third means as an initial phase pull-in point when both the first start signal and the second start signal are present. have

(Operation) The first means creates a timing extraction signal by extracting the symbol period component.

The second means detects that a symbol period component is included in a predetermined amount or more, and the third means detects that a zero-crossing point of the timing extraction signal occurs in the symbol period.

The fourth means continuously detects that a certain amount or more of symbol periodic components are included and that a zero cross point occurs in the symbol period for a certain number of periods, and converts this detection signal (first start signal) into an initial phase. This is one of the conditions for recruitment. This avoids initial phase pull-in in an unstable state of the zero cross point due to noise.

Further, the fifth means detects that the in-phase demodulated signal or the orthogonal demodulated signal is equal to or higher than a predetermined threshold, and uses this detection signal (second start signal) as one of the conditions for initial phase pull-in. do. This avoids initial phase pull-in when, for example, the automatic gain control circuit at the previous stage is not in a steady state and therefore the demodulated signal output is unstable.

By the sixth means, when both of these conditions are satisfied, the zero crossing point at that time is outputted as initial phase pull-in point information to the control circuit, and a reproduced symbol timing signal or the like is generated.

(Embodiment) Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2A and Fig. 2B are waveform diagrams showing the operation of each part thereof. An example will be explained.

The timing recovery circuit of this embodiment uses an in-phase demodulated signal X (2A-a) demodulated by a demodulator (not shown) and a quadrature demodulated signal
(2A-d) is input terminal 1 every 9.6KHz sample.
It is input to A and 1B.

The in-phase demodulated signal X (2A-a) and orthogonal demodulated signal Y (2A-d) input to the input terminals 1A and 1B are as follows.
The signal is input to the input terminals of the bandpass filters 1 a and 1 b and the in-phase/quadrature demodulated signal level determination circuit 24 .

The bandpass filter 1a and the bandpass filter 1b receive the input in-phase demodulated signal X (2A-a) and orthogonal demodulated signal Y.
Extract the component (800Hz) with twice the symbol period included in (2A-d) and (2A-b, 2A-
e), its extracted components (2A-b, 2A-e)
are input to full-wave rectifiers 2a and 2b, respectively, for full-wave rectification.

Outputs of full-wave rectifiers 2a and 2b (2A-c, 2A
-f) is added by the adder 3 and then output.
The output (2A-g) of adder 3 includes a symbol period component.

The output (2A-g) of the adder 3 is sent to the bandpass filter 4.
The bandpass filter 4 extracts a 1600 Hz component, which is a symbol period component, and outputs it (2Ah).

The symbol period component (2A-h, 2B-j) which is the output of the bandpass filter 4 is passed to the high level determination circuit 2.
0, and is input to the period determination circuit 21.

The high level determination circuit 20 determines the level of the input symbol period component (2B-j) using the level determination value "LEVEL1" (2B-j), and outputs an operation signal LEVELSW "1" to operate the gate 22.
(2B-k) is output.

The period determination circuit 21 counts the period of the falling zero cross point of the input symbol period component (2B-j), and calculates the count value Bcount (2B-l).
is output through gate 22.

Further, after outputting the count value Bcount (2B-l) to the gate 22, the period determination circuit 21 outputs a signal "LEVELSWRS" (2B-l) that resets the LEVELSW signal (2B-k) of the high level determination circuit 20.
Output.

The gate 22 is connected to the high level determination circuit 20.
The gate is operated by the LEVELSW signal "1" (2B-k), and the count value of the period determination circuit 21 is
Output Bcount to the counter 23 (2B-m).

The counter 23 compares the number of symbol periods with 6 (in the case of a sampling frequency of 9, 6KHz), and if the symbol period and the output of the gate 22 are equal, the counter 23
is counted up, and when the symbol period and the count value are not equal, the counter 23 is reset. However, if the count value of the counter 23 exceeds a certain value (2B-n, "3" in this example), the counter 23 is reset.
outputs the operation signal "1" (2B-o) to the AND circuit 25 and continues to hold the operation signal.

The in-phase demodulated signal X (2A-a) and quadrature demodulated signal Y (2A-d) input to the in-phase/quadrature demodulated signal level determination circuit 24 are level-judged by the in-phase/quadrature demodulated signal level determination value (LEVEL2), When either one exceeds the determination value, an operation signal "1" (2A-i, 2B-p) is output to the AND circuit 25.

The AND circuit 25 receives the operating signal "1" (2B-o) from the counter 23 and the operating signal "1" (2B-p) from the in-phase/quadrature demodulation signal level determination circuit 24.
When the operation start signals are both "1", the operation signal "1" is output to the switch 26 and the switch 2
Operate 6.

When the switch 26 receives the operation signal "1" from the AND circuit 25, it continues to output and hold the operation signal "1" (2B-q) for operating the control circuit 27.

The control circuit 27 receives the operation signal “1” of the switch 26.
(2B-q) starts the operation, and the control circuit 27
After the start of operation, the counter value Bcount (2B-m) of the period determination circuit 21 is inputted to the control circuit 27 through the gate 22 for the first time.
−r), the start of the regeneration timing clock,
The initial set timing regeneration circuit is operated to start correcting the phase of the regeneration timing clock.

Thereafter, the count value Bcount (2B-r) of the period determination circuit 21 passed through the gate 22 is compared with the reproduced symbol timing of the control circuit 27, and if the values deviate, the deviated count value is changed to the lead or lag of the phase. The frequency divider of the replacement control circuit 27 is switched to generate reproduced symbol timing, reproduced bit timing, and sample clock.

Figure 3 is a flow chart of this initial set timing regeneration circuit, and assuming that the timing extraction signal (hereinafter referred to as BOUT) of the output of the bandpass filter 4 in Figure 1 is:
First, step BOUT high level judgment circuit 2
Determine the level with 0 and set LEVELSW.
Next, in step, determine the fall of BOUT,
After the step, check the BOUT cycle and set it to Bcount. Further, the counter 23 is determined, and if the counter 23 is not on, the counter 23
Determine Bcount and LEVELSW and set the data. Next, determine LEVELSW
If LEVELSW is 1, the symbol rate is
Compare Bcount and find the phase lead/lag. When the above operations are completed, LEVELSW is reset to 0. In the step, the switch 26 is determined, and when the switch 26 is turned on, the control circuit 27 starts operating, and the frequency divider is operated in the step. When the switch 26 is off, the amplitude of the in-phase/quadrature demodulated signal is judged in steps, and if it is larger than a certain value (LEVEL2), the counter 23 is further judged, and if the counter 23 is on, the switch 26 is turned on. , start controlling the step frequency divider. This flowchart can be realized as is by digital signal processing.

(Effects of the Invention) Therefore, according to the present invention, the timing initial phase is set by determining the amplitude values of the in-phase and quadrature components of the phase using the in-phase and quadrature demodulated signals, In addition, when setting the timing, the symbol rate and the timing extraction signal are compared with each other in order to prevent malfunctions due to noise, etc., and the initial phase is stabilized. Therefore, when transmitting data using mobile communication such as a car phone, it is possible to create a stable timing recovery circuit for a data modem without causing the initial pull-in phase to become unstable even due to noise.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2A and B are waveform diagrams of various parts in FIG. 1, and FIG. 3 is a flowchart of this initial set timing regeneration circuit. , FIG. 4a shows a conventional timing extraction block, and FIG. 4b shows a conventional timing extraction block.
shows a conventional timing APC block. 1...BPF, 2...Full wave rectifier circuit, 3...Addition circuit, 4...BPF, 20...High level judgment circuit, 21...Period judgment circuit, 22...Gate, 2
3... Counter, 24... In-phase/orthogonal demodulation signal level determination circuit, 25... AND circuit, 26... Switch, 27... Control circuit.

Claims (1)

[Claims] 1. A first means for creating a timing extraction signal by inputting an in-phase demodulation signal and an orthogonal demodulation signal and extracting a symbol period component; a second means for detecting that the threshold has been exceeded; and determining the zero-crossing point of the timing extraction signal, and detecting the cycle length from the zero-crossing point of the falling edge of the timing extraction signal to the zero-crossing point of the next rising edge. and a third means for outputting the period length information at the zero crossing point of the falling edge; and a third means for outputting the period length information at the zero crossing point of the falling edge; fourth means for outputting a first start signal when the length is equal to the symbol period length and the level of the timing extraction signal exceeds a predetermined threshold; and determining the levels of the in-phase demodulated signal and the orthogonal demodulated signal. and a fifth means for outputting a second start signal when the level of either one exceeds a predetermined threshold; and when both the first start signal and the second start signal are present, A timing recovery circuit comprising: a sixth means for outputting a zero-crossing point of the falling edge of the timing extraction signal in the third means as an initial phase pull-in point.