JPS6166433A - Clock synchronizing circuit - Google Patents

Abstract

PURPOSE:To quicken the reception leading time and to prevent deterioration of reception characteristics by changing the operating count number of an up-down counter of a digital PLL used for synchronous detection depending on the presence of establishment of clock synchronization. CONSTITUTION:A base band signal received from an input terminal 12 is inputted to a differentiation circuit 13 and a reception clock is reproduced from the extracted reception clock component by using a digital PLL comprising a phase comparator circuit 14, an up-down counter 16, a variable frequency division circuit 17, a frequency division circuit 18, an oscillation circuit 19 and a crystal oscillator 20.An up-down counter 23 outputs an establishment of clock synchronization to a count control circuit 15 and the operation count number of the up-down counter 16 is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock synchronization circuit for a modem used in digital communications.

Conventional configuration and problems thereof FIG. 1 shows an example of a digital communication receiver using a conventional clock synchronization circuit.

The operation of this conventional example will be explained below with reference to FIG. A digital modulated signal inputted from one antenna is converted into a baseband signal by the radio receiver 2 and sent to the signal processing section 10 and the differentiating circuit 3. The differentiating circuit 3 differentiates the change point of the waveform of the received baseband signal, and the phase comparison circuit 4 compares the phase of the clock with the received recovered clock signal output from the frequency dividing circuit 9 as a received clock component. When the phase of the reproduced clock signal lags behind the received clock component, the up/down counter 6 is operated in up count mode.

When the up/down counter 5 counts up to a certain value, the variable frequency divider circuit 8, which normally operates as a 1/4 frequency divider, divides the frequency by 1/3 to advance the phase of the reproduced clock. The reproduced clock is obtained by dividing the output of the variable frequency divider circuit 8 into quarters by a frequency divider circuit 9. The clock input to the variable frequency divider circuit 80 is obtained by dividing the oscillation frequency 6 of the crystal in the oscillation frequency divider circuit 7. Note that the clock frequency of the oscillation frequency divider circuit 7 is based on the transmission clock 1.
It is set to 6 times.

Further, as a result of the determination by the phase comparator circuit 3, if the phase of the recovered clock signal is ahead of the received clock component, the up/down counter 5 operates in the down count mode, and when the up/down counter 5 counts down to a certain value, it becomes variable. The frequency dividing circuit 8 divides the frequency by one-fifth and feedback is applied so that the phase of the reproduced clock is delayed.

The signal processing unit 10 verifies the baseband signal output from the wireless receiver 2 using the reproduced clock signal output from the frequency dividing circuit 9, decodes the received data, converts it into an audio signal by D/A conversion, and outputs the signal to the speaker 11. It is output to.

The rise characteristics of the digital communication receiver described above are determined by the response characteristics of the digital PLL shown in FIGS. 3 to 9. However, in order to speed up the synchronization of the PLL, it is necessary to reduce the count setting of the up/down counter 5 and provide a large amount of feedback to the variable frequency divider circuit 8. The phase jitter of the recovered clock due to waveform distortion, S/N deterioration, etc. increases, deteriorating the data reception characteristics under normal reception conditions.

Therefore, in the conventional circuit, in order to ensure data reception characteristics up to a certain level, there is a problem in that the response of the digital PLL must be delayed at the expense of the reception rise characteristics.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a clock synchronization circuit that eliminates the problems of the prior art described above, speeds up the reception rise time, and does not cause deterioration of reception characteristics in normal reception conditions. be.

Structure of the Invention In order to achieve the above object, the present invention provides the digital
By changing the operating count of the up/down counter of the LL depending on whether or not clock synchronization is established, it is possible to obtain the effect of improving the reception rise characteristic and the normal reception characteristic.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows the configuration of parts related to synchronization, and shows 12
13 is a differential circuit, 14 is a phase comparison circuit, 15 is a counter control circuit, 16 is a receiving baseband signal input terminal;
is the first up-down counter, 17 is a variable frequency divider circuit, 1
8 is a frequency dividing circuit, 19 is an oscillation circuit, 20 is a crystal oscillator, 2
1 is a window circuit, 22 is a gate circuit, 23 is a second up/down counter, and 24 is a reproduced clock output terminal.

Next, the operation will be explained. The baseband signal received from the input terminal 12 has a waveform change timing extracted by a differentiating circuit 13. This received clock component consists of a phase comparator circuit 14, a first up/down counter 16, a variable frequency divider circuit 17, a frequency divider circuit 18, an oscillation circuit 19, and a crystal oscillator 2o.

The reception clock is regenerated by a digital PLL.

Since the operation of the digital PLL has been described in the explanation of FIG. 1, the explanation will be omitted here.

The window circuit 21, the gate circuit 23, and the second anop-down counter 23 constitute a clock synchronization determination circuit. The operation of this determination circuit will be explained with reference to FIG. In the figure, a is the received recovered clock, b is the output waveform of the window circuit produced from the received recovered clock, and C is the output of the differentiator circuit in FIG. 2B.

That is, when the reception clock is regenerated, the reception clock component output from the differentiating circuit shown in FIG. 3C becomes concentrated in the section 71 of the window waveform b.

On the other hand, if the received clock is not reliable, the phases of a and C are shifted, and as a result, C
The received clock components of are not concentrated. From this, the second
In the figure, the output of the window circuit 21 which receives the reproduced clock output from the frequency dividing circuit 18 as an input is used as the up/down setting signal of the second up/down counter 23, and the output signal of the differentiating circuit 13 is passed through the gate circuit 22 and used as the up/down setting signal of the second up/down counter 23. When the differential circuit output signal reaches the interval τ1, the up-down counter exceeds a predetermined count value and outputs a clock synchronization establishment signal to the count control circuit 16. When the second up/down counter 23 counts up to the carry output, it outputs a control signal to the gate circuit 22 to stop the clock input, so that the clock synchronization establishment signal operates stably.

The counter control circuit 16 is used to set the operational count value of the up/down counter of the digital PLL. If clock synchronization has not been established, the operation count number is set to 8, for example, and after clock synchronization is established, the operation count number is set to 32, for example. This has the advantage that the clock synchronization establishment time is shortened to one quarter compared to the case where the operation count number is fixed, and the normal reception characteristics do not deteriorate at all.

Note that in FIG. 2, the window circuit 21. Gate circuit 2
2. The clock synchronization verification circuit consisting of the second up/down counter 23 uses a method other than the method described above, for example, in FIG. It is clear that the same effect can be obtained using a method that tests .

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the operating count number of the up/down counter of the digital PLL used for synchronization verification is changed depending on whether or not clock synchronization is established, so that the reception rise time is accelerated. Moreover, there is an advantage that the reception characteristics are not deteriorated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital communication receiver using a conventional clock synchronization circuit, FIG. 2 is a block diagram of a clock synchronization circuit according to an embodiment of the present invention, and FIG. 3 is a clock synchronization verification circuit of FIG. 2. FIG. 2 is a timing diagram showing signal timing of FIG. 12...Input terminal, 13...Differentiating circuit, 14...Phase comparison circuit, 16...Counter control circuit, 16......No. 1 up/down counter, 17... variable frequency divider circuit, 18...
...Frequency divider circuit, 19...Oscillation circuit, 2o...
...Crystal oscillator, 21 ... Wind circuit,
22... Gate circuit, 23... Second up/down counter, 24... Output terminal.

Claims (1)

[Claims] It is used in a digital communication receiver, and includes a digital PLL circuit that regenerates a transmission clock, and a clock synchronization verification circuit that detects a clock component of a received signal,
By the output of the clock synchronization verification circuit, the digital PLL
A clock synchronization circuit that controls the operating count number of the up/down counter.