JPH06311155A - Clock signal extraction circuit - Google Patents

Abstract

PURPOSE:To extract a sampling clock at an optimum data sampling place at low cost by shifting the phase of a bit synchronous clock from an oscillation means in accordance with a phase difference detected in a phase comparator. CONSTITUTION:A phase difference voltage conversion circuit 4 and a phase shifter circuit 5 are cascade-connected to the output-side of the phase comparator 1. The output signal of VCO 3 is supplied to the phase shifter 5 and the sampling clock for data sampling is fetched from the circuit 5. The phase comparator 1 compares a reception signal with the clock phase of VCO 3 and detects a phase difference signal. A loop filter 2 restricts the frequency band of the detected phase difference signal. The oscillation frequency is controlled by an output signal from the loop filter 2 in VCO 3. Following speed for the change of the phase in the PLL circuit is adjusted by the loop filter 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal extraction circuit used in a LAN system or the like which is performing digital communication, and more particularly, a bit clock is extracted by a PLL circuit and received clock is used to extract received data. The present invention relates to a clock signal extraction circuit that generates a sampling clock that enables accurate sampling of data even when the clock phase of a received signal changes abruptly in a system performing sampling.

[0002]

2. Description of the Related Art Conventionally, LA has been engaged in digital communication.
In N system, as a method for achieving bit synchronization,
As shown in FIG. 5, the clock signal extracted by the PLL circuit 101 is supplied to the data sampling circuit 102 and the bit synchronization circuit 103 to perform both data sampling during reception and bit synchronization during transmission.

The PLL circuit 101 is a circuit used to extract its clock component from a received signal. As shown in FIG. 6, the phase comparator 105 and the loop filter 1 are used.
06 and a VCO (oscillator) 107.
The PLL circuit 101 detects the phase difference between the clock signal included in the received signal and the clock signal generated by the VCO 107 by the phase comparator 105, and applies a control signal corresponding to the phase difference to the VCO 107, The feedback control circuit operates to reduce the phase difference between the two signals.

Further, the PLL circuit 101 performs a follow-up operation with respect to the phase fluctuation of the clock component of the received signal, and the follow-up speed is the signal from the phase comparator 105 to VCO1.
It is adjusted by limiting the frequency band of the control signal by the loop filter (LPF; low pass filter) 106 when applying the signal to 07.

In a LAN connected in a ring shape, a signal transmitted from a certain station is received by a station connected to the downstream side of the LAN. Therefore, if the clock itself used for bit synchronization on the transmission side includes phase fluctuation, In the downstream station, clock extraction will be performed from the signal including this phase fluctuation.
The phase of the clock signal included in the received signal fluctuates depending on the pattern of the transmitted signal, and the PLL circuit 101 follows this phase fluctuation during reception.

As described above, in the LAN connected in the ring shape, a system in which the PLL circuits 101 are connected in cascade is constituted. In such a system, it is desirable that the clock signal used for bit synchronization on the transmission side does not include phase fluctuations as much as possible. Up to now, in order to suppress the phase fluctuation of the clock signal, the tracking speed of the PLL circuit 101 that is performing the clock extraction is limited, and the PLL circuits 101 are connected in cascade so that the sudden phase fluctuation does not occur, and the system is connected. I was making up.

However, if the tracking speed of the PLL circuit 101 is limited and data is sampled using the clock, the sampling position is biased when a rapid phase change occurs, and accurate sampling cannot be performed. , It was difficult to determine the appropriate tracking speed.
Therefore, as shown in FIG. 7, the PLL circuit 111 that generates a sampling clock and has a high following speed and the PL circuit that limits the tracking speed that generates a bit synchronization clock on the transmitting side are limited.
A system including the L circuit 112 is also proposed.

[0008]

However, in a system in which PLL circuits are connected in cascade, such as a ring LAN, in order to stabilize the operation of the entire system,
In order to extract the bit synchronization clock on the transmission side with a PLL circuit limited to a predetermined follow-up speed and at the same time to perform more reliable data sampling on the reception side, in the above-mentioned proposed method, 2
Since one PLL circuit is required, there is a problem in that the circuit scale becomes larger and the cost becomes higher accordingly.

The present invention has been made to solve the above-mentioned conventional problems, and its purpose is to provide a ring-shaped LA.
In a system in which PLL circuits are connected in cascade like N, data sampling can be performed more reliably and the operation of the entire system can be stabilized even if the clock phase of the received signal changes suddenly. It is an object of the present invention to provide a clock signal extraction circuit that generates a clock signal that can be generated at low cost.

[0010]

In order to achieve the above object, the first feature of the present invention is that a phase comparison means for detecting a phase difference between a clock signal and a received signal, and the clock according to the phase difference. PLL having oscillating means for generating a signal
In a clock signal extraction circuit that includes a circuit and extracts the clock signal as a bit synchronization clock of the received signal, a sampling clock is obtained by performing a phase shift of the bit synchronization clock based on the phase difference detected by the phase comparison means. Is provided with a phase shift means.

A feature of the second invention is that in the first invention, the phase shift means compares the phase with sawtooth wave signal generating means for generating a sawtooth wave signal synchronized with a sampling clock from the oscillating means. Phase difference voltage converting means for converting the phase difference detected by the means into a voltage and outputting the phase difference voltage; and voltage comparing means for comparing the sawtooth wave signal and the phase difference voltage to generate the sampling clock. It is composed of.

A feature of the third invention is that in the first invention, the PLL circuit constitutes the phase comparison means by a counter for measuring the phase difference, and the oscillation is based on the measured phase difference. It comprises a DPLL circuit provided with frequency control means for controlling the oscillation frequency of the means, and the phase shift means is provided with delay means for adjusting the phase of the bit synchronization clock from the oscillation means according to the detected phase difference. The sampling clock is delayed and output according to the phase difference.

[0013]

Since the phase difference signal itself output from the phase comparison means is not frequency limited by the frequency control means, the instantaneous phase difference between the phase of the oscillation means and the received signal can be known from this signal. . The present invention focuses on this point.

According to the above configuration, the phase of the bit synchronization clock from the oscillating means is shifted according to the phase difference detected by the phase comparator so that the phase of the bit synchronization clock is the clock phase of the received signal. The amount of deviation can be corrected, and the sampling clock having the optimum phase position for sampling the received data is generated.

Further, for example, the phase shift of the bit synchronizing clock from the oscillating means is such that the sawtooth wave signal generated from this bit synchronizing clock produces a voltage difference between the phase difference between the bit synchronizing clock detected by the phase comparing means and the received signal. This is done by extracting the time that matches the one converted to.
The phase difference between the bit synchronization clock and the received signal is linearly converted, and the coincidence point between the sawtooth wave signal and the phase difference voltage extracted by the comparison means is such that the phase angle for the sawtooth signal becomes linear with the change in the comparison voltage. Correspondingly changes. As a result, the same amount of phase shift as the detected phase difference can be applied to the bit synchronization clock.

Further, for example, by adjusting the voltage conversion coefficient of the phase difference signal taken out from the phase comparison means and the voltage slope of the sawtooth wave signal generated from the bit synchronization clock signal of the oscillation means, the phase comparison means detects it. The amount of phase shift of the generated phase difference with respect to the oscillating means can be arbitrarily adjusted, whereby the sampling clock at the optimum data sampling position can be extracted.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a clock signal extraction circuit embodying the present invention.

The clock signal extraction circuit of this embodiment is shown in FIG.
In place of the conventional clock signal extraction circuit shown in FIG.
It is used for the L circuit 101.

The phase comparator 1 and the loop filter 2 in FIG.
And VCO3 are the parts of the PLL circuit corresponding to the phase comparator 105, the loop filter 106 and the VCO 107 of the circuit shown in FIG. 6 described above, and have the same function as the conventional one of generating the bit synchronous clock signal on the transmission side. Have. The circuit of this embodiment is different from the conventional circuit shown in FIG. 6 in that the phase difference voltage conversion circuit 4 is provided on the output side of the phase comparator 1.
And the phase shifter circuit 5 are connected in cascade, and the output signal of the VCO 3 is further supplied to the phase shifter circuit 5 so that the sampling clock for data sampling is taken out from the phase shifter circuit 5.

In the PLL circuit of this embodiment, the phase comparator 1 detects the phase difference signal by comparing the received signal with the clock phase of VSO3 as in the conventional case, and the loop filter 2 detects the detected phase difference signal. A predetermined frequency band limitation is applied. VC
The oscillation frequency of O3 is controlled by the output signal from the loop filter 2. The follow-up speed with respect to the phase change of the PLL circuit is adjusted by the loop filter 2.

FIG. 2 is a block diagram showing the internal structure of the phase shifter circuit 5.

As shown in FIG. 2, the phase shifter circuit 5 includes
A sawtooth signal generation circuit 11 for generating a sawtooth signal synchronized with the output signal of the VCO 3 and a comparator 12 for comparing the phase difference voltage from the phase difference voltage conversion circuit 4 with the sawtooth signal are provided. Is used as the sampling clock. The position of the edge of the sampling clock output from the comparator 12 changes linearly with the phase angle of the sawtooth wave signal depending on whether the phase difference voltage is high or low.

Here, as shown in FIG. 3, the received signal and V
If there is a phase difference with the output signal of CO3, the phase difference is detected by the phase comparator 1, and the detected phase difference is input as a phase difference voltage to the phase shifter circuit 5 through the phase difference voltage conversion circuit 4. To be done. The phase difference voltage conversion circuit 4 has a function of voltage smoothing that allows the phase shifter circuit 5 to stably operate the phase difference signal output from the phase comparator 1, and a conversion coefficient adjustment function that adjusts the amount of voltage change. With. The phase shifter circuit 5 changes the VC according to the phase difference voltage.
A signal obtained by phase-shifting the bit synchronization clock from O3 is generated, and this is generated by the data sampling circuit 10 shown in FIG.
2 sampling clock.

FIG. 4 shows an operation timing chart of this embodiment.
Shown in.

A sawtooth signal as shown in FIG. 4 is generated from the bit synchronous clock of the VCO 3, and the sawtooth signal and the phase difference voltage (comparison voltage) are compared by the comparator 12. When the phase difference voltage is equal to the center voltage of the sawtooth wave signal b, the position of the sampling clock output from the comparator 12 occurs at the center position of the cycle of the bit synchronization clock from the VCO 3. When the phase difference voltage is as high as a, the position of the sampling clock to be output occurs at a position ahead of the center position of the clock cycle in phase. On the contrary, when the phase difference voltage is as low as b, the phase occurs at a delayed position. in this way,
The level of the phase difference voltage linearly corresponds to the phase change of the sampling clock.

According to the present invention, the phase comparator 1 is constituted by a counter for measuring the phase difference, the PLL circuit is constituted by the DPLL circuit, and the bit synchronization of the VCO 3 is performed in accordance with the phase difference signal extracted from the phase comparator 1. A means for delaying the clock signal is provided in the phase shifter 5, and the phase difference detected by the phase comparator 1 and the phase shift amount with respect to the VCO 3 are arbitrarily adjusted to extract the sampling clock at the optimum data sampling position. Good.

[0027]

As described in detail above, according to the present invention, in a system in which PLL circuits are connected in cascade, such as a ring LAN, the speed of phase fluctuation of the bit synchronization clock on the transmission side is limited. Even when the clock phase of the received signal suddenly changes, the change can be followed with sufficient speed, and data sampling can be accurately performed.

Further, a bit synchronization clock on the transmission side having different tracking speeds for the clock phase fluctuation of the received signal,
Both the sampling clock of received data and P
It can be generated by the LL circuit. Therefore, the operation of the entire system can be stabilized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock signal extraction circuit embodying the present invention.

FIG. 2 is a block diagram showing an internal configuration of a phase shifter circuit 5 shown in FIG.

FIG. 3 is a timing chart showing the overall operation of this embodiment.

FIG. 4 is a timing chart showing an operation of a main part of this embodiment.

FIG. 5 is a block diagram showing a conventional clock signal extraction circuit.

FIG. 6 is an internal configuration diagram of a conventional PLL circuit.

FIG. 7 is a block diagram showing another conventional clock signal extraction circuit.

[Explanation of symbols]

 1,105 Phase Comparator 2,106 Loop Filter 3,107 VCO 4 Phase Difference Voltage Conversion Circuit 5 Phase Shifter Circuit 11 Sawtooth Wave Generation Circuit 12 Comparator 101 PLL 102 Data Sampling Circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/08 J

Claims (3)

[Claims] 1. A PLL circuit having a phase comparison means for detecting a phase difference between a clock signal and a received signal, and an oscillating means for generating the clock signal according to the phase difference, the reception circuit receiving the clock signal. In a clock signal extraction circuit for extracting as a bit synchronization clock of a signal, a sampling clock for sampling the received signal by performing a phase shift of the bit synchronization clock based on the phase difference detected by the phase comparison means A clock signal extraction circuit comprising: 2. The phase shift means converts the phase difference detected by the sawtooth wave signal generating means, which generates a sawtooth wave signal synchronized with the sampling clock from the oscillating means, into a voltage. 2. A phase difference voltage conversion means for outputting a phase difference voltage and a voltage comparison means for comparing the sawtooth wave signal with the phase difference voltage to generate the sampling clock. The described clock signal extraction circuit. 3. The PLL circuit comprises a counter for measuring the phase difference, which constitutes the phase comparison means, and a frequency control means for controlling the oscillation frequency of the oscillation means based on the measured phase difference. The phase shift means is provided with a delay means for adjusting the phase of the bit synchronization clock from the oscillation means according to the detected phase difference, and the sampling clock is delayed according to the phase difference. The clock signal extracting circuit according to claim 1, wherein the clock signal extracting circuit outputs the clock signal.