JPS5754451A - Phase locked loop circuit for digital communication - Google Patents

Phase locked loop circuit for digital communication

Info

Publication number
JPS5754451A
JPS5754451A JP55128599A JP12859980A JPS5754451A JP S5754451 A JPS5754451 A JP S5754451A JP 55128599 A JP55128599 A JP 55128599A JP 12859980 A JP12859980 A JP 12859980A JP S5754451 A JPS5754451 A JP S5754451A
Authority
JP
Japan
Prior art keywords
bit synchronizing
phase
input terminal
digital information
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55128599A
Other languages
Japanese (ja)
Inventor
Hideshi Kenjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP55128599A priority Critical patent/JPS5754451A/en
Publication of JPS5754451A publication Critical patent/JPS5754451A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain stable internal bit synchronizing signal, by controlling the phase of a bit synchronizing signal of digital information transmitted from a transmission side and of an internal bit synchronizing signal at reception side and taking synchronism for both bit synchronizing signals. CONSTITUTION:Digital information at an input terminal 1 is applied to a wave shape circit 3 to detect edges of leading and trailing of the input digital information, and picked up bit synchronizing pulses are generated and they are applied to one input terminal of a phase comparator 4. An output pulse of a voltage controlled oscillator VCO is applied to another input terminal of the comparator 4, the circuit 4 detects the phase difference and an analog signal corresponding to the phase difference is outputted. This output is applied to a sample hold curcuit 6, and a sample hold circuit is provided at the post stage of the circuit 6, and the operation of both circuits 6, 7 are controlled with a sampling timing controller 8. Thus, the effect of phase signal caused by missing bit synchronizing pulse can be rejected.
JP55128599A 1980-09-18 1980-09-18 Phase locked loop circuit for digital communication Pending JPS5754451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55128599A JPS5754451A (en) 1980-09-18 1980-09-18 Phase locked loop circuit for digital communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55128599A JPS5754451A (en) 1980-09-18 1980-09-18 Phase locked loop circuit for digital communication

Publications (1)

Publication Number Publication Date
JPS5754451A true JPS5754451A (en) 1982-03-31

Family

ID=14988750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55128599A Pending JPS5754451A (en) 1980-09-18 1980-09-18 Phase locked loop circuit for digital communication

Country Status (1)

Country Link
JP (1) JPS5754451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166239A (en) * 1985-01-18 1986-07-26 Oki Electric Ind Co Ltd Timing recovery circuit
JPS63318848A (en) * 1987-06-22 1988-12-27 Furuno Electric Co Ltd Synchronizing signal generating circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166239A (en) * 1985-01-18 1986-07-26 Oki Electric Ind Co Ltd Timing recovery circuit
JPS63318848A (en) * 1987-06-22 1988-12-27 Furuno Electric Co Ltd Synchronizing signal generating circuit device

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