JPS576421A - Binary data modulatimg and demodulating methods - Google Patents

Binary data modulatimg and demodulating methods

Info

Publication number
JPS576421A
JPS576421A JP8204580A JP8204580A JPS576421A JP S576421 A JPS576421 A JP S576421A JP 8204580 A JP8204580 A JP 8204580A JP 8204580 A JP8204580 A JP 8204580A JP S576421 A JPS576421 A JP S576421A
Authority
JP
Japan
Prior art keywords
subdata
inputted
shift register
outputted
continuing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8204580A
Other languages
Japanese (ja)
Other versions
JPS633391B2 (en
Inventor
Teruo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8204580A priority Critical patent/JPS576421A/en
Publication of JPS576421A publication Critical patent/JPS576421A/en
Publication of JPS633391B2 publication Critical patent/JPS633391B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To make a data suitable for high-density recording, by limiting a maximum number for continuing a bit of logical ''0'', to a number as small as possible, also converting it to a signal by which the product of a minimum magnetizing inversion space and a detecting window becomes as large as possible, and recording it. CONSTITUTION:An original data is inputted to a shift register 5, is separated into each subdata by 16 bits each, and is outputted. Each subdata is inputted to a programable array logic PAL6, a maximum number of continuing a bit of logical ''0'' is limited to 3 or less, and it is divided into three converted subdata. Each of three subdata is circularly arrayed periodically, and is inputted to a shift register 7. In the register 7, the maximum number for continuing a bit of logical ''0'' is modulated so as to become an integer decided by an expression I1, or less, and it outputted from a terminal 8. Subsequently, a modulated data is converted to its original subdata by a PAL14 through a shift register 13. This subdata is inputted to a shift register 15, is shifted by the original clock, becomes its original data, and is outputted from a terminal 16.
JP8204580A 1980-06-13 1980-06-13 Binary data modulatimg and demodulating methods Granted JPS576421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8204580A JPS576421A (en) 1980-06-13 1980-06-13 Binary data modulatimg and demodulating methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8204580A JPS576421A (en) 1980-06-13 1980-06-13 Binary data modulatimg and demodulating methods

Publications (2)

Publication Number Publication Date
JPS576421A true JPS576421A (en) 1982-01-13
JPS633391B2 JPS633391B2 (en) 1988-01-23

Family

ID=13763536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8204580A Granted JPS576421A (en) 1980-06-13 1980-06-13 Binary data modulatimg and demodulating methods

Country Status (1)

Country Link
JP (1) JPS576421A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0727495U (en) * 1993-11-04 1995-05-23 モリ工業株式会社 Multi-function clothes dryer

Also Published As

Publication number Publication date
JPS633391B2 (en) 1988-01-23

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