JPS576421A - Binary data modulatimg and demodulating methods - Google Patents
Binary data modulatimg and demodulating methodsInfo
- Publication number
- JPS576421A JPS576421A JP8204580A JP8204580A JPS576421A JP S576421 A JPS576421 A JP S576421A JP 8204580 A JP8204580 A JP 8204580A JP 8204580 A JP8204580 A JP 8204580A JP S576421 A JPS576421 A JP S576421A
- Authority
- JP
- Japan
- Prior art keywords
- subdata
- inputted
- shift register
- outputted
- continuing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To make a data suitable for high-density recording, by limiting a maximum number for continuing a bit of logical ''0'', to a number as small as possible, also converting it to a signal by which the product of a minimum magnetizing inversion space and a detecting window becomes as large as possible, and recording it. CONSTITUTION:An original data is inputted to a shift register 5, is separated into each subdata by 16 bits each, and is outputted. Each subdata is inputted to a programable array logic PAL6, a maximum number of continuing a bit of logical ''0'' is limited to 3 or less, and it is divided into three converted subdata. Each of three subdata is circularly arrayed periodically, and is inputted to a shift register 7. In the register 7, the maximum number for continuing a bit of logical ''0'' is modulated so as to become an integer decided by an expression I1, or less, and it outputted from a terminal 8. Subsequently, a modulated data is converted to its original subdata by a PAL14 through a shift register 13. This subdata is inputted to a shift register 15, is shifted by the original clock, becomes its original data, and is outputted from a terminal 16.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8204580A JPS576421A (en) | 1980-06-13 | 1980-06-13 | Binary data modulatimg and demodulating methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8204580A JPS576421A (en) | 1980-06-13 | 1980-06-13 | Binary data modulatimg and demodulating methods |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS576421A true JPS576421A (en) | 1982-01-13 |
JPS633391B2 JPS633391B2 (en) | 1988-01-23 |
Family
ID=13763536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8204580A Granted JPS576421A (en) | 1980-06-13 | 1980-06-13 | Binary data modulatimg and demodulating methods |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS576421A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0727495U (en) * | 1993-11-04 | 1995-05-23 | モリ工業株式会社 | Multi-function clothes dryer |
-
1980
- 1980-06-13 JP JP8204580A patent/JPS576421A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS633391B2 (en) | 1988-01-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62269443A (en) | Parallel transmission system | |
NO20002329L (en) | Digital modulation using single sideband with suppressed carrier | |
KR840001793A (en) | Binary code modulation method, recording medium and reproducing apparatus | |
JPS6471326A (en) | Method of demodulating bi-phase signal | |
KR890001465B1 (en) | Method of recording a digital information signal on a record carrier | |
US4232388A (en) | Method and means for encoding and decoding digital data | |
GB2016245A (en) | Decoding arrangements for digital data | |
GB1381804A (en) | Digital encoding and decoding systems | |
SE8002225L (en) | METHOD AND DEVICE FOR DEMODULATING A 4-PHASE CODED DATA SIGNAL | |
JPS576421A (en) | Binary data modulatimg and demodulating methods | |
KR850005694A (en) | Binary signal bitstream conversion method and apparatus for performing the method | |
KR840002780A (en) | Pages Receiver | |
SE8009086L (en) | SET AND DEVICE FOR CODING AND DECODING DIGITAL INFORMATION | |
GB1387760A (en) | Method and apparatus for recording and reading binary digits | |
JPS576420A (en) | Binary data modulating and demodulating methods | |
ES8101827A1 (en) | Method and device for transmitting a binary sequence. | |
JPS56122251A (en) | Synchronous control system | |
JPS5739671A (en) | Shrinking system for facsimile picture signal | |
JPS5429927A (en) | Information reproducing method | |
JPS5421704A (en) | Information signal reproducers | |
JPS5710566A (en) | Decoding circuit | |
JPS54142927A (en) | Transmitter of telautogram information | |
JPS56109091A (en) | Time slot replacing system | |
KR880701047A (en) | Synchronization Detection Circuit of Digital Broadcast Receiver | |
GB1363574A (en) | Data recording and replay systems |