JPS576420A - Binary data modulating and demodulating methods - Google Patents

Binary data modulating and demodulating methods

Info

Publication number
JPS576420A
JPS576420A JP8204480A JP8204480A JPS576420A JP S576420 A JPS576420 A JP S576420A JP 8204480 A JP8204480 A JP 8204480A JP 8204480 A JP8204480 A JP 8204480A JP S576420 A JPS576420 A JP S576420A
Authority
JP
Japan
Prior art keywords
subdata
inputted
logical
shift register
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8204480A
Other languages
Japanese (ja)
Other versions
JPS6360465B2 (en
Inventor
Kunimaro Tanaka
Teruo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8204480A priority Critical patent/JPS576420A/en
Publication of JPS576420A publication Critical patent/JPS576420A/en
Publication of JPS6360465B2 publication Critical patent/JPS6360465B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Abstract

PURPOSE:To make a data suitale for high density recording, by limiting a maximum number for continuing a bit of logical ''0'', to a number as small as possible, also converting it to a signal by which the product of a minimum magnetizing inversion space and a detecting window becomes as large as possible, and recording it. CONSTITUTION:An original data is inputted to a shift register 5, is separated into each subdata by 16 bits each, and is outputted. Each subdata is inputted to a programmable array logical PAL6, a maximum number for continuing a bit of logical ''0'' is limited to <=4, and it is divided into three converted subdata. Each of three subdata is circularly arrayed periodically, and is inputted to a shift register 7. In the register 7, the maximum number for continuing a bit of logical ''0'' is modulated so as to become an integer or less defined by an expression 1, and is outputted from a terminal 8. Subsequently, a modulated data is converted to its original subdata by a PAL14 through a shift register 13. This subdata is inputted to a shift register 15, is shifted by the original clock, becomes its original data, and is outputted from a terminal 16.
JP8204480A 1980-06-13 1980-06-13 Binary data modulating and demodulating methods Granted JPS576420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8204480A JPS576420A (en) 1980-06-13 1980-06-13 Binary data modulating and demodulating methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8204480A JPS576420A (en) 1980-06-13 1980-06-13 Binary data modulating and demodulating methods

Publications (2)

Publication Number Publication Date
JPS576420A true JPS576420A (en) 1982-01-13
JPS6360465B2 JPS6360465B2 (en) 1988-11-24

Family

ID=13763509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8204480A Granted JPS576420A (en) 1980-06-13 1980-06-13 Binary data modulating and demodulating methods

Country Status (1)

Country Link
JP (1) JPS576420A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369017A (en) * 1976-11-30 1978-06-20 Nec Corp Binary data coding system
JPS5483411A (en) * 1977-12-15 1979-07-03 Nec Corp Binary data coding system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369017A (en) * 1976-11-30 1978-06-20 Nec Corp Binary data coding system
JPS5483411A (en) * 1977-12-15 1979-07-03 Nec Corp Binary data coding system

Also Published As

Publication number Publication date
JPS6360465B2 (en) 1988-11-24

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