JPS6360465B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for recording a binary information signal on or reproducing a binary information signal from a recording medium such as a magnetic tape or a magnetic disk. The present invention relates to a method of converting into a binary information signal.

FIG. 1 is a time chart showing the conventional method, and FIG. ", and T represents the bit interval. Figure 1b is the NRZ corresponding to Figure 1a.
The top of the rectangular wave shown in the figure indicates the "positive direction of magnetic flux" in the recording medium, and the bottom of the rectangular wave indicates the "negative direction of magnetic flux" in the recording medium (the same applies hereinafter).

When a record like that in Figure 1b is read out, a pulse is generated at the change point of the magnetic flux, and a signal as shown in Figure 1c is obtained, from which the signal in Figure 1b can be reproduced, and At the same time, the bit interval T can be recovered to demodulate the signal of FIG. 1b to the original binary information signal shown in FIG. 1a.

Figure 1 d is the NRZI corresponding to Figure 1 a.
Indicates recording using the (nonreturn to zero inverted) method.

In the NRZI method, the magnetic flux is changed in response to the logic "1" bit in Figure 1a (in the example shown in Figure 1, the magnetic flux changes from positive direction to negative direction, or from negative direction magnetic flux to positive direction magnetic flux). ) logic “0”
The magnetic flux does not change depending on the bit. This is explained below as 4/5NRZI, 7/8NRZI, and MFM.
The same applies to When the record in Figure 1 d is read, the pulse signal in Figure 1 e is obtained, and from this the first
It can be demodulated to the original binary information signal shown in Figure a.

When using the NRZI method, the minimum magnetization reversal interval Tmin
The logic of two consecutive bits are both “1”
This occurs when the bit interval T is equal to the bit interval T, and the maximum permissible phase error when detecting the bits of the information signal, that is, the detection window width Tw is also equal to the bit interval T.
The reciprocal of the minimum magnetization reversal interval Tmin is called the bit rate, and as the bit rate increases, the transmission bandwidth increases, and the S/N ratio of the reproduced signal deteriorates. In addition, a large detection window width Tw means that the clock pulse (that is, the bit interval T
This clock pulse is used to demodulate the reproduced signal (that is, the waveforms shown in FIG. 1e to 1d are created and the original binary information signal shown in FIG. 1a is determined from this). In this case, it means that the allowable value of the phase error between the clock pulse and the reproduced signal can be increased, and in other words, it means that the demodulation ability is increased. In the NRZI method, redundant bits are not added, so both Tmin and Tw are larger than in other methods, but if the original signal (Fig. 1a) continues to be a logic "0" signal, During this period, no pulse signal is output to the reproduced signal shown in e, making it difficult to create a clock pulse from this signal. Therefore, even if the original signal shown in FIG. Redundant bits are added and the signal is converted and recorded according to a predetermined algorithm.

In the MFM (modified frequency modulation) method, when a ``00'' bit pattern occurs in the original data string, it is recorded as a ``010'' bit pattern. FIG. 1f shows an MFM data string created corresponding to the original data string shown in FIG. 1a, and FIG. 1g shows an MFM recording corresponding to FIG. 1f.

In Fig. 1h, the original data string shown in Fig. 1a is separated into 4-bit units, 1 redundant bit is added to these 4 bits, and 5-bit data is determined by the original 4-bit bit pattern. An example of conversion to a bit pattern is shown below. The algorithm for this conversion is
An example of the algorithm used in the magnetic tape recording of the IBM Model 3420 system is shown, and the first
Figure i shows recording corresponding to Figure 1h, and this recording/reproduction method is called the 4/5NRZI method.

In Figure 1j, the original data string shown in Figure 1a is separated into 7-bit units, 1 redundancy bit is added to these 7 bits as the 7 odd-numbered bits before conversion, and the original 7 bits are separated. An example of conversion to an 8-bit bit pattern determined by the pattern is shown below. Figure 1k shows the recording corresponding to Figure 1j. This recording and playback method is called the 7/8NRZI method, and is also called the enhanced NRZI method, which is the method used in the data recorder released by Soundstream Corporation in the United States. ing. In the 4/5NRZI method shown in FIG. 1i, the maximum number Mmax of consecutive logical "0" bits after conversion is 2, and in the 7/8NRZI method shown in FIG. 1k, Nmax is 14.

Also, Electric Corporation Musashino Tsuken is considering it as an encoding method for high-density magnetic disk drives.8/9
In a system called the MNRZI system, a binary information signal input in the form of a bit series is separated into 8-bit units, and a 1-bit flag is added to the center of the 8 bits. However, in that case, if the number of logic "1" bits in the above 8 bits is 4 or more, the logic of the flag bit is set to "1", and if the number of logic "1" bits in the above 8 bits is 3 or less. In this case, the logic of the flag bit is set to "0" and the logic of the entire 9 bits is inverted. Therefore 8/9
In the MNRZI method, the maximum number of consecutive logical "0" bits is 8 or less.

As is clear from the above, in the recording and reproducing method of binary information signals, the maximum number Mmax of consecutive logical "0" bits is limited as small as possible, and the minimum magnetization reversal interval Tmin and the detection window width
It is required to convert and record a signal whose product with Tw is as large as possible. The object of the present invention is to provide a recording and reproducing method that satisfies the above-mentioned requirements better than conventional methods.

Binary information signals are normally transmitted in the form of bit series, and are recorded and reproduced in the form of bit series, but in this invention, the binary information signal input in the form of bit series is separated every n bits. 1 redundant bit is added to the signal to convert it to an (n+1) bit signal and record it.
It is similar to the NRZI method, but in this invention, n is set to 7.
When selected from any of the above numbers, the maximum number of consecutive logical 0 bits in the (n+1) bit signal string after conversion is (n+4/3-1)<m≦(n+4/ 3) Recording with higher density recording and better demodulation ability than conventional methods by using an algorithm that satisfies (1) (however, when n=7, m≦4) This is to obtain a reproduction method.

An embodiment of the present invention will be described below for the case where n=16. The data string of n=16 bits is (x ₁ ,
x ₂ ,...x ₁₅ , x ₁₆ ), and (n+1) = 17 after conversion
Let the bit data string be (z ₁ , z ₂ , ...z ₁₆ , z ₁₇ ). _{The data} string _{( x 1 , x 2 , ...} 3 sub-data (x ₁ ), 7th sub-data (x ₈ , x ₉ , x ₁₀ , x ₁₁ ), 8th sub-data (x ₁₂ , x ₁₃ ), and 9th sub-data (x ₁₄ , x ₁₅ , x ₁₆ ), and the OR output of the first sub-data is M ₁ (that is, M ₁ = x ₂ + x ₃ +
x ₄ ), the logical sum output of the second sub-data is M ₂ (that is, M ₂ = x ₅ + x ₆ + x ₇ ), and _{the fourth} sub-data is
sub-data (z ₁ , z ₂ ), fifth sub-data (z ₇ ,
z ₈ , z ₉ ) and sixth sub-data (z ₁₂ , z ₁₃ , z ₁₄ ).

The sub-data created as described above is divided into the fourth sub-data, the seventh sub-data, the fifth sub-data, the eighth sub-data, the sixth sub-data, and the ninth sub-data.
The sub-data are arranged in this order to form the converted data string (z ₁ , z ₂ , ... z ₁₆ , z ₁₇ ). FIG. 3 is a data format diagram showing the correspondence between original data and converted data in an embodiment of the present invention, where n=16
The case of the above-mentioned embodiment is shown for.

When n=16 as in the example above, m
=6. In order to limit the number of consecutive logical "0" bits in the (n+1) bit signal string after conversion to 6 or less, 2-bit subdata (for example, the 4th bit shown as No. 4 in Figure 3) is used. It is only necessary that a bit of logic "1" exists in either the sub-data of 4 bits or less (the 7th sub-data shown as No. 7 in FIG. 3) that follows this, and A combination of sub-data of bits (for example, the 6th sub-data shown as No. 6 in Fig. 3) and sub-data of 3 bits or less (the 9th sub-data shown as No. 9 in Fig. 3) that follows it. It is sufficient that a logic "1" bit exists in either of them. Now, since the 7th, 8th, and 9th subdata are still the subdata of the original signal, there is no guarantee that they contain logic "1" bits.
Since the fourth, fifth, and sixth sub-data are created according to the modulation algorithm shown in FIG. 2, they always contain logic "1" bits. That is, the second
Under the conditions shown in the figure, M ₁ ×M ₂ = 1 exists both in the first sub-data (x ₂ , x ₃ , x ₄ ) and in the second sub-data (x ₅ , x ₆ , x ₇ ). This means that a logic "1" bit is included, and M ₁ × ₂ = 1 means that the first sub-data contains a logic "1" bit, but the second sub-data does not contain a logic "1" bit. Each bit means all logic “0”, and ₁ × M ₂ = 1 is the first
This means that each bit of the sub-data is all logical ``0'', but the second sub-data includes a logical ``1'' bit, and ₁ × ₂ = 1 means that the first sub-data is This means that neither the data nor the second sub-data contains a logic "1" bit. Therefore, if the fourth, fifth, and sixth sub-data are created using the modulation algorithm shown in Figure 2 according to the above conditions, each of these sub-data will always contain a logical "1" bit. It turns out.

When Figures 2 and 3 are expressed as logical expressions, M ₁ = x ₂ + x ₃ + x ₄ (2-1), M ₂ = x ₅ + x ₆ + x ₇ (2-2), z ₁ = x ₁ ×M ₁ ×M ₂ +M ₁ × ₂ + ₁ ×M ₂ + ₁ × ₂ = ₁ + ₂ +x ₁ … (3-1), z ₂ =M ₁ ×M ₂ … (3-2), z ₃ = x ₈ ... (3-3), z ₄ = x ₉ ... (3-4), z ₅ = x ₁₀ ... (3-5), z ₆ = x ₁₁ ... (3-6), z ₇ = x ₂ ×M ₁ ×M ₂ +M ₁ × ₂ + ₁ ×M ₂ … (3-7), z ₈ = x ₃ ×M ₁ ×M ₂ +M ₁ × ₂ + ₁ × ₂ = ₂ + x ₃ ×M ₁ ...(3-8), z ₉ = x ₄ × M ₁ × M ₂ + x ₁ × (M ₁ × ₂ + ₁ × M ₂ + ₁ × ₂ ) = x ₄ × M ₁ × M ₂ + x ₁ × ₁ + x ₁ × ₂ … (3-9), z ₁₀ = x ₁₂ … (3-10), z ₁₁ = x ₁₃ … (3-11), z ₁₂ = x ₅ ×M ₁ ×M ₂ +x ₂ ×M ₁ × ₂ + x ₅ × ₁ × M ₂ + ₁ × ₂ = x ₅ × M ₂ + x ₂ × ₂ + ₁ × ₂ … (3-12), z ₁₃ = x ₆ × M ₂ + x ₃ × ₂ + ₁ × ₂ …(3-13), z ₁₄ = x ₇ × M ₂ + x ₄ × ₂ + ₁ × ₂ … (3-14), z ₁₅ = x ₁₄ … (3-15), z ₁₆ = x ₁₅ … (3 −16), z ₁₇ = x ₁₆ …(3-17).

The above has explained an example of the modulation algorithm when n = 16, but in the case of demodulation, first the logic of bits z ₂ , z ₇ , z ₈ is used to calculate the
You can understand the logic of M ₁ and M ₂ . i.e. z ₂
= 1, then M ₁ ×M ₂ = 1, ₂ ×z ₇ × ₈ = 1, then M ₁ × ₂ = 1, ₂ ×z ₇ × ₈ = 1, then ₁ ×
₂ = 1, ₂ × ₇ = 1, then ₁ × ₂ = 1, and the demodulated data is x ₁ = z ₁ × z ₂ + z ₉ × ₂ … (4-1), x ₂ = z ₂ × z ₇ + ₂ ×z ₇ ×z ₈ ×z ₁₂ ... (4-2), x ₃ = z ₂ ×z ₈ + ₂ ×z ₇ ×z ₈ ×z ₁₃ ... (4-3), x ₄ = z ₂ ×z ₉ + ₂ ×z ₇ ×z ₈ ×z ₁₄ … (4-4), x ₅ = z ₂ ×z ₁₂ + ₂ ×z ₇ × ₈ ×z ₁₂ … (4-5), x ₆ = z ₂ ×z ₁₃ + ₂ ×z ₇ × ₈ ×z ₁₃ … (4-6), x ₇ =z ₂ ×z ₁₄ + ₂ ×z ₇ × ₈ ×z ₁₄ … (4-7), x ₈ = z ₃ … (4-8), x ₉ = z ₄ … (4-9), x ₁₀ = z ₅ … (4-10), x ₁₁ = z ₆ … (4-11), x ₁₂ = z ₁₀ … (4-12), x ₁₃ = z ₁₁ … (4-13), x ₁₄ = z ₁₅ … (4-14), x ₁₅ = Z ₁₆ … (4-15), x ₁₆ = z ₁₇ … (4 −16).

As explained earlier, the converted data (z ₁ ,
z ₂ , . . . z ₁₆ , z ₁₇ ), the maximum number of consecutive logic "0"s is 6 bits or less.
Therefore, the method of this invention is the 7/8NRZI method,
Compared to the 8/9MNRZI method, the logic “0” after conversion
The consecutive maximum values of bits of are sufficiently reduced to (n
(When n=16, m=6; When n=10, m=4) Regeneration of the clock becomes extremely easy. In the case of modulation, equations (2-1), (2-2) and equations (3-1) to (3-17) are used, and in the case of demodulation, equations (4-1) to (4-1) are used.
16) is a simple logic conversion shown in PAL (Programmable Array Logic), which is currently commercially available.
You can easily configure the hardware by using the following. Furthermore, n=16 is a unit of words in a computer, etc., and performing 16/17 conversion as described above is a conversion in units of words, which is convenient in practice.

FIG. 4 is a block connection diagram showing an embodiment of the present invention, where a shows a modulation section and FIG. 4b shows a demodulation section. In the figure, 1 is the input terminal of the original data,
2 and 11 are input terminals of the original clock, 4 and 12 are sub-clock generators, 5 and 13 are serial input parallel output shift registers, and 6 and 14 are programmable clock generators.
Array Logic (hereinafter abbreviated as PAL), 7,
15 is a parallel input serial output shift register, 8 is a modulated data output terminal, and 16 is an original data output terminal.

The subclock generator 4 receives the original clock and generates a subclock every 16 bits. The original data is input from the serial input terminal of the shift register 5, and is separated into first, second, and third sub-data from the parallel output terminal every 16 bits and output.

Each sub-data is input to PAL6 and the formula (2-
1), (2-2) and formulas (3-1) to (3-
17), the fourth, fifth, and sixth sub-data, namely (z ₁ , z ₂ ), (z ₇ , z ₈ , z ₉ ), (z ₁₂ ,
8 bits (z ₁₃ , z ₁₄ ) are created. Each sub-data is arranged in the order of 4th, 7th, 5th, 8th, 6th, and 9th sub-data as shown in FIG.
It is input from the parallel input terminal of the shift register 7. The subclock obtained from the subclock generator 4 is used as the load timing signal for this input. By shifting the signal input to the shift register 7 in this way using the modulation clock (a clock with a frequency of 17/16 of the original clock), modulation data can be obtained from the serial output terminal 8, and this modulation data can be used for recording. can.

Next, the above recording is reproduced to obtain modulation data and a modulation clock. The sub-lock generator 12 receives the modulation clock and generates a sub-clock every 17 bits. Modulated data is input from the serial input terminal of the shift register 13, and is separated into seventh, fifth, eighth, sixth, and ninth sub-data and output from the parallel output terminal every 17 bits. The 4th, 5th, and 6th sub data are input to PAL12, and the formula (4
-1) to (4-16), the first to third sub-data are created, arranged in the order of the first, second, and third sub-data, and input in parallel to the shift register 15. Input from the terminal. The subclock obtained from the subclock generator 12 is used as the load timing signal for this input. The original data can be obtained from the serial output terminal 16 by shifting the signal input to the shift register 15 using the original clock (a clock with a frequency of 16/17 of the modulation clock).

In general, one way to evaluate the modulation method used in magnetic recording and reproducing devices is to take the maximum number of consecutive logical "0" bits Nmax on the horizontal axis, and plot it on the vertical axis.
It is displayed as a position on the coordinates of Tmin×Tw (normalized to Tmin×Tw in the NRZI method). FIG. 5 is a coordinate position diagram showing the effect of this invention, and in this invention, n=10, n=
16 case and MFM, NRZI, 4/5NRZI, 7/8
The coordinate positions for each NRZI method are shown.

As is clear from FIG. 5, according to this invention, Tmin×
Tw can be increased, that is, modulated data suitable for high-density recording can be obtained.

[Brief explanation of the drawing]

Figure 1 is a time chart showing the conventional method.
FIG. 2 is a logic diagram showing an example of the logic used to create sub-data in this invention, and FIG. 3 is a data format diagram showing the correspondence between original data and converted data in an embodiment of this invention. FIG. 4 is a block connection diagram showing one embodiment of this invention, and FIG. 5 is a coordinate position diagram showing the effects of this invention. 1... Original data input terminal, 2, 11... Original clock input terminal, 3, 10... Modulation clock input terminal, 4, 12... Sub clock generator, 5, 13... Series input parallel Output shift register, 6, 14...PAL, 7, 15...Parallel input serial output shift register, 8...Modulation data output terminal, 16...Original data output terminal.

Claims (1)

[Claims] A step of separating a binary information signal input in the form of a 1-bit series into every n bits, where n is a predetermined number selected from among arbitrary integers of 7 or more. , among the above n-bit original data, the specific 3 bits (x ₂ , x ₃ , x ₄ ) are the first subdata, and the other specific 3 bits (x ₅ , x ₆ , x ₇ ) are the second subdata. Sub data, and another specific 1 bit (x ₁ ) as third sub data, M ₁ = x ₂ + x ₃ + x ₄ , M ₂ = x ₅ + x ₆ + x ₇ , z ₁ = ₁ + ₂ + x _{1 ,} z ₂ = M ₁ × M ₂ , _{z 7} = _{x 2} XM ₁ × M ₂ + M ₁ × _{2 + 1} × M ₂ , z ₈ = _{2 + 2} +x ₁ × ₁ +x ₁ × ₂ , z ₁₂ = x ₅ × M ₂ + x ₂ × ₂ + ₁ × ₂ , z ₁₃ = x ₆ × M ₂ + x ₃ × ₂ + ₁ × ₂ , z ₁₄ = x ₇ × The _{fourth sub} -data _{z 1 , z 2} , and _the fifth
sub-data z ₇ , z ₈ , x ₉ and the sixth sub-data
Conversion sub-data creation step that defines z ₁₂ , z ₁₃ , z ₁₄ , the first, second,
and excluding 7 bits of third sub-data (n-
7) Divide the bit data into 3 or less pieces of sub-data and insert each of them between two adjacent pieces of conversion sub-data in the circular array of the above-mentioned 3 pieces of conversion sub-data to convert (n+1) bits. In _the modulation stage to create _the subsequent data, _{M 1 ×}
Determine the logic of M ₂ , M ₁ × ₂ , ₁ × M ₂ , ₁ × ₂ , and according to this determined logic, the fourth, fifth,
From each of the sixth conversion sub-data, x ₁ = z ₁ × z ₂ + z ₉ × ₂ x ₂ = z ₂ × z ₇ + ₂ × z ₇ × z ₈ × z ₁₂ x ₃ = z ₂ × z ₈ + ₂ ×z ₇ ×z ₈ ×z ₁₃ x ₄ =z ₂ ×z ₉ + ₂ ×z ₇ ×z ₈ ×z ₁₄ x ₅ =z ₂ ×z ₁₂ + ₂ ×z ₇ × ₈ ×z ₁₂ x ₆ =z ₂ ×z ₁₃ + ₂ ×z ₇ × ₈ ×z ₁₃ x ₇ = z ₂ ×z ₁₄ + ₂ ×z ₇ × ₈ ×z ₁₄ demodulation into the above first, second, and third sub-data A method for modulating and demodulating binary data, comprising a demodulation step.