JPS60241353A - Code converting system - Google Patents

Abstract

PURPOSE:To eliminate the generation of a DC component and to reduce circuit scale by converting each bit of an input data bit sequence to a two-bit binary code and allowing ''1'' and ''0'' of an obtained data sequence to correspond to inversion and non-inversion respectively. CONSTITUTION:When a data bit sequence A which has a bit pattern, which generates DC components, and includes 5 continuous bits is supplied to a shift register 1 in the MEM system, the third and following bits out of 5 bits are converted to two bits ''10'', ''00'', and ''10'' respectively by a converting circuit 5, and a conversion result B different from that in the MFM system is obtained. Output data of the converting circuit 5 is modulated in accordance with the NRZI system to obtain a write signal C which does not include DC components.

Description

TECHNICAL FIELD The present invention relates to a code conversion system used when transmitting data in a band-limited transmission system in which data is recorded at high density on a recording medium.

BACKGROUND ART Various modulation methods have been proposed and put into practical use for recording or transmitting data at high density on recording media such as magnetic tapes, magnetic disks, and even optical disks. These various modulation methods, especially those that can record at higher density than other methods, divide the data string into consecutive blocks of m bits each, and convert the m-bit binary code in each block into m-bit binary code. Code conversion to convert to code and 2 obtained after code conversion
NRZI (Non
-Ratu,rn to Zero Iavtryg
) Or it can be treated as a combination with NRZ modulation. In general, a modulation method for recording at high density on a recording medium is required to satisfy the following conditions.

(1) The minimum inversion interval (hereinafter referred to as Tmin) of the write signal waveform to the recording medium obtained after modulation is long and the maximum inversion interval (hereinafter referred to as Tmax) is short. T
r! If LLrL is long, the interference between adjacent inversions will be reduced, making it possible to achieve higher density, and if TmαX is short, self-synchronization will be easier (+D Used to detect recording focus from signals reproduced from recording media) The detection window width (hereinafter T
It is written as W. ) is wide. In magnetic recording, recording bits are detected by detecting the peak of the reproduced signal waveform, but since the TW is the tolerance for the deviation of the peak position, a wider TW is suitable for high-density recording. Furthermore, in a recording/reproducing device using a laser beam, when the TW is wide, the permissible range of deviation of the detection position becomes wide, and the amplitude at the detection point becomes large, so that the noise margin becomes large.

(iiD DC and low frequency components do not exist in the write signal to the recording medium obtained after modulation. In devices with a transmission system that cannot transmit DC and low frequency components, the waveform of the signal containing these components will be distorted. Furthermore, in a recording/reproducing device using laser light, these components degrade the reliability of the system.

On the other hand, if these components do not exist, it becomes possible to remove low frequency noise and drift mixed in by the IS filter.

MFM (Modified Ffequtr
The LcyMocltL, Latio1'L) method is known. Code conversion in this MFM system is performed based on a conversion table as shown in Table 1. That is, for example, the first
Each pip)d in the input data bit sequence as shown in Figure (5).

is a 2-bit binary code α depending on the state of the previous pick) j. ho, and a code sequence as shown in FIG. 3(c) is obtained. The obtained code sequence is modulated by NR and ZI to obtain a write signal S1 as shown in FIG.

Here, in order to estimate the DC component in the write signal obtained as described above, the accumulated charge will be calculated. The cumulative charge is assumed to be +1 for the positive minimum width, -1 for the negative minimum width, and ±2 for twice the base width, and then counted. It can be obtained by The amount of DC component can be estimated depending on the magnitude of this accumulated charge.

Now, in the write signal shown in FIG. 10, the sum of the high level sections in the part corresponding to the input data series "0110" is IT, and the sum of the low level sections is 3T, so the cumulative charge is -2. Note that T indicates the inverse number (bit period) of the data bit transfer rate. Therefore, if the input data series is a series of "0110", the cumulative charge may be negative infinity, and a DC component may exist.

In the MFM method, input data bit sequences can be classified into the following five types of sequences.

(α) °"00" (II) "01...10" (number of consecutive 1's: odd number) (ty) "01...10n (number of consecutive 10's: even number) @ ) "1...1""
(Number of consecutive 1s: odd number) ($) “1...
・A DC component occurs only in the write signal corresponding to the series (c) among the five series of 1" (10 consecutive pieces: even number) or more.

Therefore, we developed a modulation method M2 that does not generate a DC component in the write signal.
) method, ZM (Zero Moclu, 1ation
) method, the method disclosed in Japanese Patent Laid-Open No. 150110/1983 (hereinafter referred to as M method), and the like have been proposed.

In each of these systems, improvements have been made to the code conversion for the sequence (C). That is, first, in the M2 method, almost the same conversion as in the MFM method is performed, but if an even number of pits 1"' are consecutive after the bit "o" and the accumulated charge up to the bit "o" is not zero, then , the last pit '1'' is converted to correspond to non-inversion. For example, each bit in the input data bit series as shown in FIG. 2(G) is converted into a 2-bit binary code as shown in FIG. 2(C). The obtained code sequence is modulated by NRZI to obtain a write signal S2 as shown in FIG. As is clear from FIG. 0, in the <M2 method, the accumulated charge of the write signal becomes zero and no DC component is generated. However,...

In the M2 system, T77LαX becomes 3T, and MF
It has the disadvantage that it is longer than Tmax (2T) in M.

Next, in the ZM method, the input data bit sequence is divided into 2 bits for each bit so that the accumulated charge does not exceed ±3.
The resulting code sequence is modulated by NRZ I. For example, if the input data bit series is
When the result is as shown in Figure (5), each bit is converted into a 2-bit binary code as shown in Figure (C). The obtained code sequence is modulated by NRZI to obtain a write signal S3 as shown in FIG. Also in this ZM method, the accumulated charge becomes zero and no DC component is generated. However,
In this ZM method, the look-ahead property is the bit in the data focus sequence from the data bit to be converted to the next data bit (0) that appears next.
Since a value obtained by counting '1# is required, a memory with a large storage capacity is required, which has the disadvantage that the circuit scale of the modulator becomes large.

Next, in the M method, when the input data bit sequence becomes as shown in FIG. 4(5), each bit is converted into a 2-bit binary code as shown in FIG. 4(c).

The obtained code sequence is modulated by NRZI and
A write signal S4 as shown in is obtained. In this M method, the accumulated charge becomes zero and no DC component is generated, but
Tmil becomes sail 5T and Tm in MP'M system
It has the disadvantage of being shorter than i n (l T ).

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to improve Trnax and T1'rLin.
It is an object of the present invention to provide a code conversion method which is equivalent to MFM, has no direct current component in the obtained write signal, and can reduce the circuit scale of a modulator/demodulator.

The code conversion method according to the present invention converts each bit in a two-bit series of input data into one of "00," 01, and "10," or a two-bit number with a turn, depending on the state of the bit before each bit. It is characterized in that it is converted into a binary code, and in the resulting data series, 1'' corresponds to inversion and 0'' corresponds to non-inversion.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 5 to 16.

In FIG. 5, each bit in a data bit series containing information such as audio information is sequentially applied to the serial input terminal of a 5-bit shift register 1 at a predetermined period. A clock c1 is supplied to the shift clock input terminal of the shift register 1 from the clock generation circuit 2 in synchronization with the data bits applied to the serial input terminal. Each time data bits are applied by this clock C1, they are sequentially stored in the shift register 1. Here, it is assumed that each data bit stored in the shift register 1 is sequentially shifted by clock C in the direction of the least significant bit ct-2. At this time, the most significant bit d in the 5-bit binary code derived to the parallel output terminal of shift register 1
+2 is supplied to the P(A) generation circuit 3 and the P(C) generation circuit 4. In the P(6) generation circuit 3, bit d+2 is applied to one input terminal of an AND (logical product) gate G1 and an OR (logical product) gate G2.

The output of the AND gate G is applied to the D input terminal of the D-type frizzo flop F1. A clock C1 output from the clock generation circuit 2 is applied to the clock input terminal of the D-type flip-flop F1. The Q output and the Q output of this D-type frizzo flop F are respectively OR gate G.
A and the other input terminal of AND gate G1. The output of the OR gate G2 is supplied to the conversion circuit 5 as the output P(6) of the P(5) generation circuit 3.

On the other hand, in the P@ generation circuit 4, the pitch "+2" is applied directly to one input terminal of the AND gate G3, and at the same time, is applied to one input terminal of the AND dart G4 via the inverter ■nυ.These AND gates G3 and G4
Each output is applied to the D input terminal of the D-type Frino Frozzo F2 via the OR dart G5. A clock C4 is applied to the clock input terminal of the D-type frizzo float fF2. The Q output and Q output of this D-type flip-flop F2 are applied to the other input terminals of AND gates G and G4, respectively. At the same time, the Q output of this D-type flip flop F2 becomes the output P@ of the P@ generation circuit 4.
The signal is then supplied to the conversion circuit 5.

The conversion circuit 5 contains the lower three bits (d) of the 5-bit binary code derived to the parallel output terminals of the shift register. ,
LL-,d, is also supplied. The conversion circuit 5 is formed of a ROM (read-only memory) or the like in which data is written in advance based on a conversion table such as Table 2, for example. α from this conversion circuit 5. , ho are output and applied to parallel input terminals of a 2-bit shift register 6. A clock C1 is applied to the parallel set clock input terminal of the shift register 6, and a clock C2, which is multiple outputted from the clock generation circuit 2 at a period of μ of the clock C1, is applied to the shift clock input terminal. Two bits of output data from the conversion circuit 5 are simultaneously set in the shift register 6 by the clock C1. Thereafter, each bit a forming the data set in this shift register 6. ,h.

are sequentially outputted from the serial output terminals in response to the clock C2 and applied to one input terminal of the exclusive OR gate G6. The output of the exclusive OR dart G6 is applied to the D input terminal of the D-type Frizzo Frozzo F3.

A clock C2 is applied to the clock input terminal of the D-type frig front panel F3. The Q output of this D-type frizzo F3 is applied to the other input terminal of the exclusive OR f-) G6. An NRZI modulator is formed by these exclusive OR gate G6 and D-type frizzo-flop F3, and the Q of this D-type frizzo-flop 7''F3 is
The output is output as a write signal S5.

In the above configuration, when the bit d+2 supplied from the shift register 1 to the P(6) generating circuit 3 changes as shown in FIG. 6(g), bits d, +, and d. As shown in the same figure (G) and 0, respectively, the pitch is +2 and the clock C.
Changes that are delayed by one clock and two clocks of 1 occur.

In P(8) generation circuit 3, bit d+2 is supplied to one input terminal of 0 rate G2, so bit c
When L+2 becomes °'1", the output P(5) also becomes ttl".

Also, for D type Frizzo Frozzo F, bit '+2 is '1''
The set state is reached when the first clock C1 is generated after . When the D-type frisog frozzo F1 enters the set state, the output of the AND gate G becomes low level, so that the D-type frisog frozzo F is reset when the first clock C4 is generated after entering the set state. Therefore, the D-type flip-flop F' is alternately set and reset each time the clock C1 is generated when the bit cl+2 is Ill-- fir. The Q output of this D-type flip-flop F1 is 0
Since it is supplied to the other input terminal of Rr-to G2,
The output P(A) is as shown in Fig. 6 [F]; )'+2
The state depends on whether the number of ``1''s existing between 0'' when becomes from 1'' to 0'' and the par 0'' before this ``0'' is odd or even.

That is, °′1″ that exists between tlon and “0”
When the number of outputs P(6) is an odd number, the output P(6) becomes 1'' immediately after the pitch ``+2'' changes from 1'' to 0''. Conversely, when the number of II III existing between tt On and P0 is an even number, the output P(8) will change from Pip'+2 to "1".
Immediately after changing from `` to 0'', it becomes ``o''.

Furthermore, in the P@ generating circuit 4, when bit d is +2 II III, the state of the D-type flip-flop F2 does not change. When bit d+2 is IIO, jl, D-type frinozo flop F2 is inverted when clock C4 occurs. Therefore, the output P0 is bit d+ as shown in FIG.
2 is reversed when clock C4 is generated when It O71, and when bit d+2 is l'', it does not change and the previous value is maintained. Therefore, '' in the bits before bit d+2 in the input data bit series When the number of 0'' is odd, the output P@ becomes Pa1''.
When the number of O7Fs is even, the output P@ becomes II O11.

These outputs P(g), P(Bl together with bits d-o-L
: When L-2 is supplied to the conversion circuit 5, the conversion circuit 5 changes bit a as shown in 0 and 0, respectively. and ho are output. A write signal S5 is obtained by modulating the output data of the conversion circuit 5 according to the NRZ I method.

Here, in the encoder according to the present invention as described above, in the MFM method, a data bit sequence in which a DC component occurs, that is, <10
A case will be described in which a data bit sequence having a bit pattern in which an even number of "1"s exist between II and °'0# is supplied. First, it is assumed that a data bit series having a bit pattern as shown in FIG. 7(5) and containing five consecutive bits is supplied to the shift register 1. Also, if the number of 0'' from the beginning to the second bit of the consecutive 5 bits is an odd number, the output P when converting the 3rd and 4th bits from the beginning of the consecutive 5 pins.
Assume that @ is 1''. Then, from the conversion circuit 5 that generates data according to the conversion table as shown in Table 2, the same figure (
Data as shown in c) is output 2 bits at a time and code conversion is performed. In this code conversion, each bit after the third from the beginning of the five consecutive bits is “
10", "oo" at l Q 71, which is a different conversion from the MFM method. The output data of the conversion circuit 5 is modulated by the NRZI method and becomes 0 in the same figure. As shown, a write signal containing no DC component is obtained.

Next, it is assumed that a data bit series having a bit pattern as shown in FIG. 8(6) and containing five consecutive bits is supplied to the shift register 1. Also, the data from the first bit to the second bit of these consecutive 5 bits is
It is assumed that the number of ``'' is an odd number and the output P(c) becomes u1'' when converting the third and fourth bits from the beginning of the five consecutive bits. Then, the conversion circuit 5
From this, data as shown in FIG. 3(C) is output 2 bits at a time and code conversion is performed. In this code conversion, the third and fourth bits from the beginning of the five consecutive bits are respectively °l 00 B, It 10 #,
This is a 2-bit code, which is a different conversion from the MFM method.

The output data of the conversion circuit 5 is modulated by the NRZI method, and a write signal containing no DC component is obtained as shown in FIG.

Above, we have explained the case where the number of 1'' between pa0'' and pa0'' is 2, but to 1u between '鴴''' and uO'''
The case where the number of objects is 4 or more will be explained.

First, it is assumed that a data bit series having bit numbers and turns as shown in FIG. 9(g) and containing 6 consecutive bits is supplied to the shift register 1. Also, if the number of "θ" up to the first bit of these 6 consecutive bits is an odd number, the output P(c) will be '1'' when converting the second and subsequent It 1 'Jj bits from the beginning. Then, the conversion circuit 5 outputs data as shown in FIG.

In this code conversion, the 4th and 5th focus from the beginning of consecutive 6 bitotos, that is, consecutive (L
Of the 131 bits, the last bit and the last bit are converted into 2-bit codes of 11007+ and u10#, respectively.

1 from the last of these consecutive II 111 bits
The conversion of the previous bit and the last bit is different from the conversion according to the MFM method. The output data of the conversion circuit 5 is modulated by the NRZI method, and a write signal containing no DC component is obtained as shown in FIG.

Here, 6 bits including 1 bit following the 5th focus shown in FIG. 8(5), ie, FIG. 10(5) or FIG. 11(
When code conversion is performed on consecutive 6 bits with the bit strings shown in Figure 10 (c) or 11.
Data as shown in Figure ◎ is obtained. Then, the 10th
A write signal as shown in FIG. 0 or FIG. 11 is obtained, the inversion interval is 2T or 2.5T, and TnαX is 2.5T.
becomes.

Furthermore, as is clear from FIGS. 7 and 8, two different types of conversion are performed on the four bits having the bit turn "0110"' depending on the state of the bit immediately before it. This prevents the generation of write signals that cannot be decoded.

In other words, bit no or turn "00" as shown in Figure 7-4.
If the conversion as shown in FIG. 8(c) is also performed on the 5 bits having 110", the data bit series as shown in FIG. 12(5) is supplied to the shift register 1. A large number of data as shown in FIG. 1 are outputted from the conversion circuit 5, and a write signal is formed which is inverted every <2T as shown in FIG. 0, making decoding impossible.

In addition, a bit turn as shown in FIG.
0110'', the waveform of the write signal becomes the 9th bit.
The waveform of the write signal becomes similar to that shown in FIG. 0, and decoding becomes impossible.

Further, in a bit sequence having a bit pattern such that the number of consecutive 1''' between 0'' and 0'' is an even number of 4 or more, as shown in FIG. The last and last tt 1 m of 1" are converted to par 10" and "oo", respectively, as in the code conversion shown in FIG. 7, and a code string as shown in FIG. 13 (G) is obtained. If formed, the Tm1n of the write signal becomes 0.5 T, which is not preferable, as shown in FIG. 130. still,
At this time, not only the last two bits of the continuous a1'' but also other bits are converted in the same way to form a code sequence as shown in FIG. 14(C) and to obtain a write signal as shown in FIG. Such a conversion is equivalent to that in the ZM system, and requires a large-capacity buffer to latch all consecutive °'s.

FIG. 15 shows a decoder that restores the data encoded by the encoder of FIG.

In Fig. 15, each bit in the code sequence is sequentially 1
It is stored in the 0-bit shift register 7.

The parallel output of this shift register 7 is supplied to a conversion circuit 8. The conversion circuit 8 is formed of a ROM or the like in which data is written in advance based on a conversion table such as Table 3, for example. This conversion circuit 8 forms the original data bit sequence. is output.

FIG. 16 shows another example of a decoder in which each bit in the code sequence is sequentially stored in a 6-bit shift register. The parallel output of this shift register 9, ie, bit α. , ho, αIn hbα2.b2 is supplied to the conversion circuit 1o.Conversion circuit 1O
is the bit ISo at the parallel output of shift register 9
bit d forming the original data bit sequence. At the same time, outputs e and e2 are generated according to the truth table as shown in Table 4. Output e is bit h in the parallel output of shift register 9. is applied to the reset input terminal of the flip-flop corresponding to bit h2 and the set input terminal of the flip-flop corresponding to bit h2, and at the same time, bit b is applied via gate G7 having an OR function.
, is applied to the set input terminal of the flip-flop corresponding to . Therefore, when this output e occurs, bit h□
+ '1 and h2 ha, 7FLPi"I-"0",
ul'' and 1'''. Further, the output e2 is the parallel output signal h of the shift register 9. It is applied to the set input terminal of the flip-flop corresponding to bit b2 and the reset input terminal of the flip-flop corresponding to bit b2, and simultaneously applied to the set input terminal of the flip-flop corresponding to bit 61 via gate G7. Therefore, when this output e2 occurs, bit h. , bl and h2 become ul"ul" and 'o#, respectively.

Effects As detailed above, in the code conversion method according to the present invention, the bit of the first value in the data bit sequence is changed to 600'' and ulo according to the state of the previous bit.
``Which one of ``600'' converts to a 2-bit binary code with one pit pattern and converts the bit of the second value in the data pinto sequence to that bit depending on the state of the previous bit.

Since it is converted into a 2-bit binary code having a pitch) no f turn of either 1 of '01# and tt 10 m, the bit/P that would generate a DC component when code conversion by the MFM method is performed. It is also possible to perform code conversion on a data bit sequence having turns so that no direct current component is generated. At the same time, Tmax and T
rnt and rL can be made equivalent to the MFM method.

Furthermore, in the code conversion method according to the present invention, continuous I
Since it is not necessary to latch all t171, a large-capacity buffer memory or the like is not required, and the circuit scale of the encoder can be reduced.

Table 1 Table 2 Table 3 Table 4

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of code conversion in the MFM system, Figure 2 is a diagram showing an example of code conversion in the M2 system, Figure 3 is a diagram showing an example of code conversion in the zMM system, and Figure 4 is a diagram showing an example of code conversion in the zMM system. is a diagram showing an example of code conversion in the M method,
5 is a waveform chart showing the operation of the device shown in FIG. 5, FIG. 5 is a waveform chart showing the operation of the device shown in FIG. FIG. 15 is a block diagram showing an example of a decoder that restores data encoded by the encoder of FIG. 5, and FIG. 16 is a block diagram showing another example of the decoder. Applicant Pioneer Co., Ltd. Patent Attorney Motohiko Fujimura 9 Figures 10 Figures (A+ 7 0 / / 0 0 (8) 010000t θ 00 10 No. 11 I ¥ 1 C Kiri 10/IQl (8' Ot 0000 to 000) # ＞/Figure 2 (A) 0 0 / / 0 0 / / 0 (B)
00 to 00 10 DO10001000 13
Diagram (A) (17/ / / / 0 (B) 000101'10t) 010 pieces! Figure 4 (A) Ol l l I 0 CB) DO1000tODO10 #, Figure 15

Claims (3)

[Claims] (1) The bit of the first value in a data sequence consisting of a binary code is
Converting the data into a 2-bit binary code having a pit turn of either 00# or '10', and converting the bit of the second value in the data sequence to that bit according to the state of the previous bit string. "00", '01' and 10
'1n of the obtained data series.
A code conversion method characterized in that tt Ojl corresponds to inversion and tt Ojl corresponds to non-inversion. (2) the first value is "+" and the second value is l
The code conversion method according to claim 1, characterized in that: ”. (3) In principle, ``1'' of the data series consisting of the binary code is 2-bit 2 having the bit pattern ``01''.
Convert to base code and convert '0' to '00' and 1 as a general rule.
Convert to a 2-bit binary code with a bit pattern of one of 10'', provided that the pit start turn of the consecutive 5-bit binary code is uoollo'' and the 5-bit binary code is Q Q II, “
Convert to a 2-bit binary code having each bit pattern of 10#, and if the bit pattern of the 5-bit binary code is "10110" and the third bit from the beginning of the 5-bit binary code If the number of preceding 0'' bits is an odd number, the third and fourth bits from the beginning of the 5-bit binary code are set to ``00'', respectively.
, '10'' into a 2-bit binary code with each bit pattern, and consecutive rules (r
L is an even number of 4 or more 2. The code conversion method according to claim 1, wherein each previous bit is converted into a 2-bit binary code having a bit pattern of IO"."00".