JPS6355152B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for recording a binary information signal on or reproducing a binary information signal from a recording medium such as a magnetic tape or a magnetic disk. The present invention relates to a method of converting into a binary information signal.

FIG. 1 is a time chart showing the conventional method, and FIG. ", and T represents the bit interval. Figure 1b is the NRZ corresponding to Figure 1a.
The top of the rectangular wave shown in the figure indicates the "positive direction of magnetic flux" in the recording medium, and the bottom of the rectangular wave indicates the "negative direction of magnetic flux" in the recording medium (the same applies hereinafter). When a record like that in Figure 1b is read out, a pulse is generated at the change point of the magnetic flux, and a signal as shown in Figure 1c is obtained, from which the signal in Figure 1b can be reproduced, and At the same time, the bit interval T can be recovered to demodulate the signal of FIG. 1b to the original binary information signal shown in FIG. 1a.

Figure 1 d is the NRZI corresponding to Figure 1 a.
Indicates recording using the (nonreturn to zero inverted) method.

In the NRZI method, the magnetic flux is changed in response to the logic "1" bit in Figure 1a (in the example shown in Figure 1, the magnetic flux changes from positive direction to negative direction, or from negative direction magnetic flux to positive direction magnetic flux). ), logic “0”
The magnetic flux does not change depending on the bit. This is explained below for 4/5NRZI, 7/8NRZI, MFM
The same applies to When the record in Figure 1 d is read, the pulse signal in Figure 1 e is obtained, and from this the first
It can be demodulated to the original binary information signal shown in Figure a.

When using the NRZI method, the minimum magnetization reversal interval T _nio occurs when the logic of two consecutive bits are both "1" and is equal to the bit interval T, and is also the maximum allowable phase error when detecting bits of an information signal. That is, the detection window width T _w also becomes equal to the bit interval T. The reciprocal of the minimum magnetization reversal interval T _nio is called the bit rate, and as the bit rate increases, the transmission bandwidth increases, and the S/N ratio of the reproduced signal deteriorates. Also, a large detection window width _Tw means that the reproduced signal (for example, the pulse shown in Figure 1e)
A clock pulse (that is, a pulse with a bit interval T) is created from the clock pulse, and the reproduced signal is demodulated using this clock pulse (that is, the waveform shown in FIG. 1 d is created from the pulse shown in FIG. 1 e, and from this the waveform shown in FIG. When determining the original binary information signal), this means that the tolerance for the phase error between the clock pulse and the reproduced signal can be increased, which in turn means that the demodulation capability is increased. In the NRZI method, redundant bits are not added, so both T _nio and T _w are larger than in other methods. During this period, no pulse signal is outputted to the reproduced signal shown in FIG. 1e, making it difficult to generate a clock pulse from this signal. Therefore, the first
Even if the original signal shown in Figure a has consecutive logical ``0'' bits for a long time, redundant bits are added so that the number of consecutive logical ``0'' bits is less than a predetermined number in the recorded signal. , signals are converted and recorded according to a predetermined algorithm.

In the MFM (modified frequency modulation) method, when a "00" bit pattern occurs in the original data string, it is recorded as a "010" bit pattern. FIG. 1f shows an MFM data string created corresponding to the original data string shown in FIG. 1a, and FIG. 1g shows an MFM recording corresponding to FIG. 1f.

In Fig. 1h, the original data string shown in Fig. 1a is separated into 4-bit units, 1 redundant bit is added to these 4 bits, and 5-bit data is determined by the original 4-bit bit pattern. An example of conversion to a bit pattern is shown below. The algorithm for this conversion is
An example of the algorithm used in the magnetic tape recording of the IBM Model 3420 system is shown, and the first
Figure i shows recording corresponding to Figure 1h, and this recording/reproduction method is called the 4/5NRZI method.

In Figure 1j, the original data string shown in Figure 1a is separated into 7-bit units, 1 redundant bit is added to these 7 bits as 7 odd parity bits before conversion, and the original 7 bits are divided into 7 bits. An example of conversion to an 8-bit bit pattern determined by the pattern is shown below. Figure 1k shows the recording corresponding to Figure 1j. This recording and playback method is called the 7/8NRZI method, and is also called the enhanced NRZI method, which is the method used in the data recorder released by Soundstream Corporation in the United States. ing. In the 4/5NRZI method shown in FIG. 1i, the maximum number N _nax of consecutive logical "0" bits after conversion is 2, and in the 7/8NRZI method shown in FIG. 1k, N _nax is 14.

As is clear from the above, in the recording and reproducing method of binary information signals, the maximum number N _nax of consecutive logic "0" bits is limited as small as possible, and the minimum magnetization reversal interval T _nio and the detection window Width T _w
It is required to record the signal by converting it into a signal whose product is as large as possible. The object of the present invention is to provide a recording and reproducing method that satisfies the above-mentioned requirements better than conventional methods.

Binary information signals are normally transmitted in the form of bit series, and are recorded and reproduced in the form of bit series, but in this invention, the binary information signal input in the form of bit series is separated every n bits and divided into n bits. It adds one redundant bit and converts it to an (n+1) bit signal for recording.
It is similar to the NRZI method, but in this invention, n is set to 4.
When choosing from among the above arbitrary even numbers, by using an algorithm such that the maximum number of consecutive logical 0 bits _Nnax in the (n+1) bit signal after conversion is n/2. The present invention provides a recording and reproducing method that has higher density recording and better demodulation ability than conventional methods.

An embodiment of the present invention will be described below for the case where n=16. The data string of n=16 bits is (x ₁ ,
x ₂ ,...x ₁₅ , x ₁₆ ), and (n+1) after conversion
= 17-bit data string (z ₁ , z ₂ ......z ₁₆ , z ₁₇ )
shall be. _{The data string ( x 1 , x 2 ,} ...... _{z 3 = x 4 , z 4 _ _ _ _ _} = x ₅ , z ₆ = x ₇ , z ₈ = x ₉ , z ₉
Depending on the correspondence of = x ₁₀ , sub data (z ₃ , z ₄ ......
z ₉ ), z ₁₂ = x ₁₁ , z ₁₃ = x ₁₂ , z ₁₄ = x ₁₃ ,
Sub-data (z ₁₂ , z _{13 ,} z ₁₇ ) is created by the correspondence of z ₁₅ = x ₁₄ , z ₁₆ = x ₁₅ , z 17 = x ₁₆ . Sub data (z ₁ , z ₂ ) and sub data (z ₁₀ , z ₁₁ ) are created by. However, (z ₁ , z ₂ )=(z ₄₁ ,
z ₄₂ ) as the fourth sub-data, (z ₁₀ , z ₁₁ )=(z ₅₁ ,
z ₅₂ ) will be referred to as the fifth sub-data.

Figure 2 is a logic diagram showing the logic of formula (1), and the fourth
Given the subdata of and the fifth subdata, The first sub-data can be determined by .

As is clear from equation (1) or FIG.
When the second bit (z ₂ ) of the fifth sub-data is logic “0”, the first bit (z ₁₀ ) of the fifth sub-data
is always logic "1", and when the first bit (z ₁₀ ) of the fifth sub-data is logic "0", the second bit (z ₂ ) of the fourth sub-data is always logic "1". . From this, it can be seen that the maximum number of consecutive logical "0" bits N _nax after conversion by this method is eight.

FIG. 3 is a data format diagram showing the correspondence between the original data and the data after conversion in an embodiment of the present invention.
sub-data, second sub-data, fifth sub-data, and third sub-data are arranged in this order.

FIG. 4 is a block connection diagram showing an embodiment of the present invention, where a shows a modulation section and FIG. 4b shows a demodulation section. In the figure, 1 is the input terminal for the original data, 2,
11 is the original clock input terminal, 3 and 10 are the modulation clock input terminals, 4 and 12 are sub-clock generators, 5 and 13 are serial input parallel output shift registers, and 6 and 14 are programmable array logic (hereinafter referred to as PAL). ), 7 and 15 are parallel input and serial output shift registers, 8 is an output terminal for modulated data, and 16 is an output terminal for original data. Also, 21, 22, 23, 24, 25 are the first,
The transmission lines of the second, third, fourth, and fifth sub-data are shown.

The subclock generator 4 receives the original clock and generates a subclock every 16 bits. The original data is input from the serial input terminal of the shift register 5, and is separated into first, second, and third sub-data from the parallel output terminal every 16 bits and output.
Of these, the first sub-data is input to PAL6,
Fourth sub-data and fifth sub-data are created according to the logic of equation (1). The fourth sub-data, the second sub-data, the fifth sub-data, and the third sub-data are arranged in the above order and inputted from the parallel input terminals of the shift register 7. The sub-clock obtained from the sub-clock generator 4 is used as the load timing signal for this input. The signal input to the shift register 7 in this way is converted into a modulating clock (a clock with a frequency of 17/16 of the original clock).
If shifted by , modulated data is obtained from the serial output terminal 8, and this modulated data can be used for recording.

Next, the above recording is reproduced to obtain modulation data and a modulation clock. The subclock generator 12 receives the modulation clock and generates a subclock every 17 bits. Modulation data is in shift register 13
The data is inputted from the serial input terminal of the sub-data, and is separated into fourth, second, fifth, and third sub-data and output from the parallel output terminal every 17 bits. Of these, the fourth and fifth sub-data are input to the PAL 12, and the first sub-data is created according to the logic of equation (2). The first sub-data, second sub-data, and third sub-data are arranged in the above order and inputted from the parallel input terminals of the shift register 15. The subclock obtained from the subclock generator 12 is used as the load timing signal for this input. The original data can be obtained from the serial output terminal 16 by shifting the signal input to the shift register 15 using the original clock (a clock with a frequency of 16/17 of the modulation clock).

In the above embodiment, n is an even number, and the number of bits of the second and third data is (n/2-1) and (n/2-2), respectively. It is not limited to the distribution of numbers, and any distribution is possible. Therefore, in general, n may be an odd number or an even number. However, since logical "0" bits may occur consecutively in each of the second and third sub-data, the difference in the number of bits between the second and third sub-data (1 bit in the above embodiment) is It is preferable to make the distribution as small as possible.

Furthermore, we explained the case where n=16, but when n is 4
It goes without saying that this invention can be applied to any of the above integers. However, if n=4, the second
Either the sub-data or the third sub-data disappears (that is, the number of bits becomes zero).

In general, one way to evaluate the modulation method used in magnetic recording and reproducing devices is to take the maximum number of consecutive logical "0" bits N _nax on the horizontal axis and
It is displayed as a position on the coordinate axis with T _nio × T _w (displayed normalized to T _nio × T _w in the NRZI method). FIG. 5 is a coordinate position diagram showing the effect of this invention, and in this invention, n=8, n=16
The coordinate positions are shown for the case of , and for each method of MFM, NRZI, 4/5NRZI, and 7/8NRZI.

As is clear from Fig. 5, according to this invention,
It is possible to increase T _nio ×T _w while keeping the value of N _nax sufficiently small, that is, it is possible to obtain modulated data suitable for high-density recording.

[Brief explanation of the drawing]

Figure 1 is a time chart showing the conventional method.
FIG. 2 is a logic diagram showing an example of the logic used to create sub-data in this invention, and FIG. 3 is a data format diagram showing the correspondence between original data and converted data in an embodiment of this invention. FIG. 4 is a block connection diagram showing one embodiment of this invention, and FIG. 5 is a coordinate position diagram showing the effects of this invention. 1... Original data input terminal, 2, 11... Original clock input terminal, 3, 10... Modulation clock input terminal, 4, 12... Sub clock generator, 5, 13... Series input parallel Output shift register, 6, 4...PAL, 7, 15...Parallel input serial output shift register, 8...Output terminal for modulated data, 16...Output terminal for original data.

Claims (1)

[Claims] A step of separating a binary information signal input in the form of a 1-bit series into every n bits, where n is a predetermined number selected from among arbitrary integers of 4 or more; A step of decomposing the n-bit data into first, second, and third sub-data, and constructing the first sub-data from specific three bits x ₁ , x ₂ , x ₃ of the n-bit data. , 2-bit fourth sub-data (z ₄₁ , z ₄₂ ) and 2
The fifth sub-data (z ₅₁ , z ₅₂ ) of the bit are respectively z ₄₁ = x ₁・(x ₂ +x ₃ ) ₊₂・₃ z ₄₂ =x ₂ +x ₃ z ₅₁ =x ₂・(x _{2 +} ) ₊₂・₃ z ₅₂ =x ₃・(x ₂ +x ₃ )+x ₁・₂・₃ , the step of determining and configuring the fourth sub-data, the second sub-data, and the second sub-data. 1. A method for recording and reproducing a binary information signal, comprising the step of recording (n+1) bit data arranged in the order of the sub-data No. 5 and the third sub-data on a recording medium in the form of bit series. 2 When the integer n is an even number, the second sub-data is made up of specific (n/2-1) bits out of the n-bit data, and the third sub-data is made up of the first bit out of the n-bit data. 3 bits of sub-data and the above (n/2-1) of the second sub-data
2. A method for recording and reproducing a binary information signal according to claim 1, characterized in that the method is composed of bits other than bits.