JPH0422061B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD This invention relates to an information conversion method, and particularly to an information conversion method suitable for use when recording or transmitting a digital signal and converting it into a signal suitable for the recording system or transmission system. Background technology and its problems For example, in a device that converts audio signals into PCM and performs magnetic recording using a rotating head without forming a guard band, the differential output characteristics of magnetic recording and low-frequency crosstalk from adjacent tracks In addition, since the rotary transformer cuts off low frequency components, there is a problem in that faithful reproduction of low frequencies cannot be achieved. Therefore, in such a device that has a narrow recording/reproducing frequency band and is required to have few low frequency components, it is possible to modulate the recording signal using a modulation method that has few frequency spectrum components in the low frequency component or DC component region. An example of such a modulation method is the so-called NRZI, which is effective. This is to invert the signal when it is "1" in the data signal, and not to invert it when it is "0". However, in this NRZI modulation method,
If "0" continues, the modulation signal is no longer inverted during that time, resulting in a disadvantage that the frequency decreases and the DC component and low-frequency component increase. Therefore, the PCM information is broken down into an arbitrary number of bits, and each bit is converted into a larger number of bits to prevent a large number of consecutive "0"s. In addition, when trying to perform the above-mentioned recording using a small device such as a portable device, it is necessary to downsize the rotating head,
Due to the narrowing of the recording track, there are problems such as a poor S/N ratio of the reproduced output and a narrow recording band. Here, for example, with respect to S/N, it is desirable that the ratio between the detection window width (T _W ) during demodulation and the minimum inversion width (T _nio ) be as small as, for example, twice or less. Therefore, for example, a conversion method called the Gabor code has been proposed. The Gabor code converts 2 bits (B ₁ , B ₂ ) of information into 3 bits (P ₁ , P ₂ , P ₃ ), and the conversion formula is P ₁ = _3p + B ₁ + ₂・B _1f P ₂ =P _3p・₁ +B ₂ P ₃ = _3p +B ₁ +B _2However , p in the saphix is the previously converted information, f is the next converted information, and the demodulation formula is B ₁ = _3p・P _1p It is given by +P _3p・P ₁・P ₃ B ₂ =P ₂・P. In this Gabor code, T _W = 0.67T, T _nio
= 0.67T, T _nax (maximum inversion width) = 1.33T (where T is the time or wavelength equivalent to 1 bit of modulated data), where the ratio of T _W and T _nio is 1. Furthermore, a conversion method called 4/5 conversion has also been proposed. 4/5 conversion method is 4 bits (B ₁ , B ₂ , B ₃ , B ₄ )
The information is converted into 5 bits (P ₁ , P ₂ , P ₃ , P ₄ , P ₅ ), where the number of consecutive "0"s is 2 or less in NRZI representation. That is, among the combinations of 5 bits, there are 17 combinations in which "0" is not consecutive at the beginning or end, and the number of consecutive "0"s is 2 or less between them. Therefore, the 4 bits of modulated data (0000) ~
(1111) can be changed to any of the 17 ways mentioned above.
Convert by matching 16 ways one to one. In this way, conversion can be performed such that the number of "0"s between "1"s is always 2 or less. In this 4/5 conversion method, T _W = 0.8T, T _nio =
0.8T, T _nax =2.4T, where the ratio of T _W and T _nio is 1. However, in these methods, a DC component exists in the signal after NRZI conversion. If there is a DC component in the modulated signal, that is, the recorded signal, then the original signal as shown in FIG. 1A, which should originally be reproduced as shown in FIG. 1B, will be In reality, as shown in Figure 1C, the DC component is offset and reproduced to 0, and the output signal becomes a signal whose time axis has been varied as shown in Figure 1D, resulting in a faithful signal. Digital waveform reproduction is not possible. For this reason, since the frequency and the like are determined taking these into consideration, there have been problems such as the inability to increase the recording density. On the other hand, for example, 16/20 conversion, 24/30 conversion, etc. can perform conversion without a DC component. However, in these methods, the constraint bit length required for both conversion and inverse conversion becomes extremely long, the device becomes extremely large, and error propagation is large, making it impractical. Furthermore, T _nio and T _nax correspond to the lower and upper limits of the recording signal frequency, respectively, and if this ratio is too large, problems will occur in terms of frequency characteristics and the like. Therefore, this ratio needs to be about 3 times or less. OBJECTS OF THE INVENTION In view of the above points, the present invention provides an information conversion system that can reduce the direct current component to substantially zero and has a short constraint bit length. Summary of the Invention In the present invention, when converting 6-bit information to 8-bit information, the 8-bit information is
In the signal after NRZI modulation, the same level should be continuous for 3 bits or less, and the above 8.
A first combination in which the DC accumulation in the bits is 0, a second combination in which the DC accumulation is +2 or -2, and the 6-bit information is the combination selected under the above conditions and 1. When the second combination is used, the positive or negative sign of the DC accumulation is stored, and when the second combination is used next, the DC accumulation is This information conversion method converts the first bit of the second combination described above so that it has a sign opposite to that in memory, and the DC component is made substantially zero to improve the bit error rate. , high-density recording becomes possible. Embodiment Hereinafter, an embodiment of the present invention will be described in detail based on FIGS. 2 to 6. Here, 6 bits (B ₁ , B ₂ , B ₃ , B ₄ , B ₅ ,
B ₆ ) information in 8 bits (P ₁ , P ₂ , P ₃ , P ₄ , P ₅ ,
P ₆ , P ₇ , P ₈ ), the possible forms of 6-bit information (B ₁ to B ₆ ) are 2 ⁶ = 64
That's right. On the other hand, for 8 bits (P ₁ to _{P 8} ), in order to remove the DC component, first of all, if 4 bits out of 8 bits are positive (1) and 4 bits are negative (0) in the signal after NRZI modulation, then good. Note that in order to set T _nax /T _nio =3, the condition is that the number of consecutive "0"s in the NRZI representation is 2 or less, that is, the number of consecutive "0"s in the modulated signal is 3 or less at the same level. Considering these conditions, we further consider that the number of first or last “0” is 0 or 1 in NRZI representation.
The number of combinations in each case is as shown in Table 1 below.

[Table] From Table 1, it is possible to ensure that the number of consecutive "0"s is 2 or less even in the connection part between 8-bit patterns, that is, the boundary part, for example, if the number of first "0" is 1 or less. This is the case when the number of the last "0" is one or less. However, in this case, the number of combinations is only 19+9+12+6=46. This is less than the number of 64 combinations of 6 bits, and with other selection methods the number would be even smaller. Therefore, combinations other than DC component 0 will be considered. That is, for example, when the number of the last "0" is one or less, the number of combinations based on the number of the first "0" and the amount of accumulated DC is as shown in Table 2 below.

[Table] Here, regarding the accumulated amount of DC, for example, as shown in FIG. 2, the case where the previous combination ends in negative (0) is the case. Therefore, if the previous combination ends with a positive (1), the positive and negative signs are reversed. Further, for example, for a combination in which the leading bit is "0", if this leading bit is converted to "1", the sign of the DC accumulation is reversed as shown in FIG. So, for example, the accumulation of DC in Table 2 is +2, -
2, the first bit is "0", 8+10=18 combinations are used, and the above-mentioned 46 first combinations without DC component and this second 18 combinations are used.
The street corresponds one-to-one with 64 6-bit combinations. Each time the second combination appears, the first bit is converted so that the DC accumulation is alternately positive and negative. In other words, as shown in Fig. 4, when the second combination appears, count the number of inversions P (the number of "1"s) from the second bit, and calculate the number of times until the next second combination appears. If the number of inversions is an even number, the first bit (arrow) is converted to "1" as shown in FIG. 4A, and if it is an odd number, it remains as "0" as shown in FIG. 4B. Even if this causes an accumulation of +2 or -2 DC, this will be canceled out by the next second combination, and the DC component will become 0 in the long run no matter what combination is continued. Examples of specific codes (combinations) created based on Table 2 above are shown in Tables 3 and 4 below.
Note that Table 3 shows 46 first combinations, and Table 4 shows 18 second combinations.

【table】

【table】

【table】

[Table] In Table 4 above, when the polarity of the previous DC accumulation information Q' is positive, the code on the left, in which the DC accumulation is -2, is used, and when it is negative, the DC accumulation is +2. The code on the right is used. FIG. 5 is an example of a device that performs conversion according to the above-described method. In the figure, 1 is an input terminal, 2 is a 6-bit shift register for input, 3 is a conversion logic, and 4 is an 8-bit shift register for output.
The information supplied to the input terminal 1 is transferred 6 bits at a time through the shift register 2 by pulses applied to the clock terminal 5 at the data bit rate, and the 6 bits (B ₁ to B ₆ ) of information are transferred to the conversion logic 3. is supplied to With this conversion logic 3, the above 1
A to-to-one conversion is performed and the converted 8 bits (P ₁
~ _P8 ) is supplied to the shift register 4. Furthermore, the number of inversions of the signal after conversion is detected. Here, since the number of inversions is known in advance for each combination, for example, information on the number of inversions is stored in the read-only memory that constitutes the conversion logic 3 (it is only necessary whether the number of inversions is an odd number or an even number; for example, if it is an odd number, it is "1").
It is possible to simultaneously output corresponding outputs.
This output Q is supplied to a latch circuit 6, and this latch output Q' is supplied to a conversion logic 3. Furthermore, the timing of the pulses supplied to the clock terminal 5 at the data bit rate is determined by the timing detection circuit 7.
This timing signal is supplied to the load terminal LD of the shift register 4 and the latch terminal of the latch circuit 6 every six bits of data. When converted to the first combination described above, the output 8 bits are output as they are to the shift register 4, and the number of inversions P of the output first combination and the input from the latch circuit 6 are According to Q', output Q is taken out as information on DC accumulation as shown in Table 5 below. In other words, when the DC accumulation is zero (DC = 0), if the number of inversions P is an even number (“0”), the value of the input Q' from the latch circuit 6 is taken out as is as the output Q, and each latch circuit 6
is latched and transmitted to the next combination. Also, at this time, if the number of inversions P is an odd number (“1”), the value of the input Q' from the latch circuit 6 is taken out as the output Q with its polarity reversed, and the value is latched to the latch circuit 6. and transmitted to the next combination. Note that this output Q can be easily determined using the following equation. Q=(Q'+DC+(-1) ^P ...(1)

[Table] Also, when converted to the second combination, the 8 bits of the output of the conversion logic 3 are transferred to the latch circuit 6.
Depending on the polarity of input Q' from Q', the first bit is converted to "1" or "0", and based on the number of inversions P, etc., the output is output as DC accumulation information as shown in Table 6. taken out.

【table】

[Table] In other words, if the polarity of the input Q' from the latch circuit 6 is positive, the amount of accumulated DC up to that point is +2, so the accumulation of DC in the current combination is controlled in the direction of -2. It is preferable that the first bit be inverted and set to "1". Therefore,
At this time, the shift register 4 is supplied with information in which only the leading bit is inverted to "1". Furthermore, if the value of the input Q' from the latch circuit 6 is negative, the amount of accumulated DC up to that point is -2, so it is preferable to control the accumulation of DC in the current combination in the direction of +2. Then, the first bit is inverted and set to "1". At this time, information on the accumulation of direct current is transmitted as follows. That is, in Table 6, the accumulation of DC is +2 (DC=+
In case 2), if the number of inversions P is an even number (“0”), the value obtained by adding +2 to the value of the input Q′ from the latch circuit 6, and if the number of inversions P is an odd number (“1”) If so, the value of input Q' from latch circuit 6 is +2
are added and the polarity is reversed, and the output Q
and latched them to the latch circuit 6, respectively.
It is transmitted to the next combination as DC accumulation information. On the other hand, when the DC accumulation is -2 (DC=-2), if the number of inversions P is an even number, the value obtained by adding -2 to the value of the input Q' from the latch circuit 6, and the number of inversions P If is an odd number, -2 is added to the value of the input Q' from the latch circuit 6, the polarity of which is reversed, and the value is taken out as the output Q and latched to the respective latch circuits 6, and is used as DC accumulation information. Transmit to the next combination. In other words, in this case as well, the output Q can be obtained based on 1 above. However, if the absolute value of (Q'+DC) exceeds the maximum value that can be transmitted at that time, the maximum value is set as the output Q. However, in this case, the information that can transmit the DC accumulation only needs to be 1 bit, and the output Q can be considered to be 1 or -1 corresponding to the DC accumulation +2 or -2. If the added value of -2 exceeds 1 or -1, the value will be limited to that value. Incidentally, in Table 6, the value of the output Q marked with a circle indicates this. In this way, the second combination receives information on the DC accumulation up to the previous combination and serves to control its leading bit so that the DC accumulation approaches zero. Returning to FIG. 5 again, the contents converted to 8 bits and taken into the shift register 4 as described above are sequentially read out by a clock signal with a frequency 4/3 times that of the input signal supplied from the clock terminal 8. It will be done. This read signal is supplied to the JK flip-flop circuit 9, and an NRZI modulated signal is taken out from the flip-flop circuit 9 to the output terminal 10 by the clock signal from the terminal 8 applied to the clock terminal of the flip-flop circuit 9. It will be done. FIG. 6 shows an example of a device for demodulating, and in the same figure, the signal from the input terminal 11 is
The data is supplied to the 8-bit shift register 13 through the NRZI demodulation circuit 12, and transferred in the shift register 13 in 8-bit units by the pulse of the code bit trace from the clock terminal 14. Information (P ₁ to _{P 8} ) from this shift register 13 is supplied to the conversion logic 15. Then, demodulation is performed by the above-mentioned one-to-one inverse conversion, and the demodulated information (B ₁ to _{B 6} ) is supplied to the shift register 16, and the timing detected by the timing detection circuit 17 from the pulse of the clock terminal 14 is Each time a signal (pulse for each block) is applied to the load terminal LD of the shift register 16, it is taken in. The contents of shift register 16 are then shifted by pulses applied to clock terminal 18 at the data bit rate and taken out at output terminal 19. Note that when 8 bits are supplied by the above-mentioned second combination, the first bit is ignored and the inverse conversion is performed. Conversion and demodulation can be performed in this way. In this method, T _W =T _nio =0.75T,
T _nax =2.25T. Here, the Gabor code mentioned above has the disadvantage of an increase in low-frequency components due to the spread of T _nax , but this disadvantage is offset by the absence of DC components in this method, resulting in a better Recording and playback can be performed. Also, compared to the 4/5 conversion method mentioned above, T _W is a little inferior, but since this method has no DC component, there is no time axis fluctuation of the reproduced signal mentioned above, and recording and reproduction at higher frequencies is possible. Therefore, the recording density can be increased. Furthermore, unlike the 16/20 conversion and 24/30 conversion described above, the constraint bit length does not become long. Effects of the Invention As described above, according to the present invention, in the signal after NRZI modulation, the number of successive bits of the same level is 3 or less, and the first one in which the accumulation of DC in the 8 bits of conversion information is 0. A second combination of DC accumulation and +2 or -2 is made, and the 6 bits of the information to be converted are made to correspond one-to-one with the combination selected under the above conditions, and the second combination is In contrast, the first bit is inverted every time it appears, so the DC component becomes zero in the long run, improving the bit error rate, enabling high-density recording, and shortening the constraint bit. It is particularly useful for use in rotary head type recording apparatuses, etc., in which a modulation method with a large T _W , T _nax /T _nio of 3 or less, and a small amount of low-frequency components is appropriate.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the conventional method.
FIGS. 2 to 4 are diagrams for explaining the present invention, FIG. 5 is a block diagram showing an example of a converter used in this invention, and FIG. 6 is a diagram showing an example of a demodulator used in this invention. FIG. 1 is an input terminal, 2 and 4 are shift registers, 3 is a conversion logic, 5 and 8 are clock terminals, 6 is a latch circuit, 7 is a timing detection circuit, 9 is a flip-flop circuit, and 10 is an output terminal.

Claims (1)

[Claims] 1. When converting 6-bit information to 8-bit information, the above-mentioned 8-bit information is set so that the number of successive bits of the same level is 3 or less in the signal after NRZI modulation, and the above-mentioned 8-bit information is A first combination in which the DC accumulation is 0, and a second combination in which the DC accumulation is +2 or -2, and the 6-bit information is one-to-one with the combination selected under the above conditions. When the second combination is used, the sign of the DC accumulation is stored, and when the second combination is used next, the DC accumulation is stored. An information conversion method that converts the first bit of the second combination described above so that it has the opposite sign.