JPH0783273B2 - Code converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code conversion device for realizing a Run Length Limited code suitable for recording a digital signal.

2. Description of the Related Art When recording digital data at high density on a magnetic tape or disk, a run length limited code (hereinafter referred to as an RLL code) is usually used. The RLL code converts an m-bit data word into an n-bit code word, and converts the converted n
A code that limits the number of consecutive bits of the same binary value in a bit string obtained as a result of connecting code words of bits to d or more and k or less.

Assuming that the 1-bit length of a data word is T, the following three points are known as conditions desired for an RLL code suitable for high density recording.

(1) The detection window width Tw (= m / nT) is large.

(2) The minimum inversion interval Tmin (= d · Tw) is large.

(3) The maximum continuous bit number k is small.

As the detection window width Tw is large, the influence of time axis fluctuations such as jitter and peak shift in the reproducing process on the decoding error rate is small, and the larger the minimum inversion interval Tmin is, the higher the frequency component of the recording / reproducing system is cut off. The less the maximum continuous bit number k is, the easier it is to obtain the self-clocking function to extract the clock information from the reproduced signal as the maximum continuous bit number k is less affected by the characteristics. However, the self clock function can be sufficiently obtained.

In addition to the above three points, in the case of a digital video signal which is usually represented by 8 bits, it is desired that a data word can be converted into a code word in units of 8 bits in order to avoid error propagation in the decoding process. .

Conventionally, various RLL codes have been developed from the above viewpoint.
Franaszek et al., USP 3,689,899) is one of them. According to the above definition, the 2/3 conversion code is d = 2, k =
RLL code satisfying 9 and switching between conversion of a 2-bit data word into a 3-bit code word and conversion of a 4-bit data word into a 6-bit code word, Tw = 0.
667T is a variable length RLL code.

Problems to be Solved by the Invention The 2 / 3-transform RLL code is an excellent RLL code that satisfies the above conditions (1) to (3) well.
It also uses conversion. For this reason, in code conversion of digital image data represented by, for example, 8 bits, a data word may be divided into two words of image data of 1 bit of 8 bits. In such a case, an error of one code word at the time of decoding is propagated (expanded) to two words of 8-bit image data.

Although the RLL code is used for the purpose of not deteriorating the decoding error rate even when performing high-density recording, since the 2/3 conversion code is a variable length RLL code, the decoding error is rather enlarged. I will end up. Especially for home digital VTRs
For example, due to the necessity of recording for a long time, the recording density has been increased to a point near the limit. Therefore, the number of codeword errors in the reproduction process is very large, and error propagation (expansion) frequently occurs. This is a serious problem that must be resolved.

Means for Solving the Problems The present invention provides the following new means in order to solve the problems of the above conventional example.

A code conversion device for converting an 8-bit data word to a 12-bit code word, the same binary value in a bit string obtained by connecting 12-bit code words of a code conversion output to an 8-bit data word input. 2 or more consecutive bits of 10
To limit to the following, a codeword generating means for generating at least one 12-bit codeword for the 8-bit data word input, and a first selecting means for selecting an output of the codeword generating means. And delay means for delaying the output of the code word selecting means, and second selecting means for selecting the output of the delay means.

Operation The present invention has realized a means for controlling either or both of the preceding code word W1 and the code word W2 following W1.
As a result, the number of code words that make up an RLL code has increased more than before, and an 8-bit data word is directly converted to a 12-bit code word to realize an RLL code that satisfies the restriction of d = 2, k = 10. (Tw = 0.667T).

EXAMPLES Next, the present invention will be described in detail using examples. In addition,
For convenience of explanation, in order to classify the code words CW used in the present invention, parameters representing the characteristics of the code words as shown in FIG. 2 are defined. That is, L block: the start end of a codeword in which 1-bit same binary value TB continues.

R block: The end of a codeword in which r bits of the same binary value LB are consecutive.

B block: The middle part of a codeword of b (= 12-l-r) bits.

The code words CW used in the present invention are limited to those satisfying the following conditions.

(I) 1 ≦ l ≦ 9, 1 ≦ r ≦ 9 (II) The B block completely satisfies the d, k restriction.

(III) means that 0 and 1 of d bits or more and k bits or less continue alternately in the B block (except b = 0). Furthermore, the following parameters F and E are introduced for l and r.

F = 0 (l = 1), F = 1 (2 ≦ l ≦ 5), F = 2 (6 ≦ l ≦ 9), E = 0 (r = 1), E = 1 (2 ≦ r ≦ 5) , E = 2 (6 ≦ r ≦ 9) The connection between the codewords is controlled based on the four parameters (TB, F, E, LB) defined in this way. Regarding the connection between the first code word W1 and the second code word W2 shown in FIG. 3, the R block of the code word W1 and the L block of the code word W2
This means that the d, k constraint is also satisfied in the block connection part. Below, the rule regarding the connection of these codewords is called the connection rule.

Table 1 shows the code word combination rule in the present invention, which is defined based on the four parameters (TB, F, E, LB). In Table 1, CW-No is a combination number of code words and an identification number of code words forming the combination, and the same data word is made to correspond to the code words forming one combination.

TB, F, E, and LB in Table 1 are parameters relating to codewords, and EXAMPLE shows an example of codewords that can be represented by the parameters. Next, the codeword combination rule in Table 1 will be described in detail. In addition, in order to clarify the combination of code words, the code words will be described below using the notation CW (F, E, LB). In addition, the code word CW (F, E, LB) in which 1 is replaced with 0 and 0 is replaced with 1 is code word CW
It is called the back pattern of (F, E, LB) and is written as CW (F, E, LB) ′.

(1.1) Codeword CW of F ≠ 1, E ≠ 1, TB = 1, LB = 1 (F, E,
1) is the back pattern CW (F, E, 1) 'and CW (F, E, 1)
The code word CW (F, E, 0) in which the values of F, E, TB are equal and LB = 0,
Combine with its back pattern CW (F, E, 0) ′.

(CW-No = 1.1,1.2,1.3,1.4,4.1,4.2,4.3,4.4,13.1,13.
2,13.3,13.4,16.1,16.2,16.3,16.4) (1.2) The code CW (F, 1, X) of F ≠ 1, E ≠ 1, TB = 1 is
Combine with its back pattern CW (F, 1, X) '. In addition,
X represents both 0 and 1.

(CW-No = 2.1, 2.2, 3.1, 3.2, 14.1, 14.2, 15.1, 15.2) (1.3) Codeword CW with F = 1, E ≠ 1, TB = 1, LB = 1 (1, E,
In 1), the values of CW (1, E, 1) and F, E, TB are equal, and they are combined with the codeword CW (1, E, 0) of LB = 0.

(CW-No = 5.1,5.2,6.1,6.2,11.1,11.2,12.1,12.2) (1.4) Codeword CW (1,1, X) with F = 1 and E = 1 and its backside pattern CW (1, 1, X) 'does not combine with other code words, but corresponds to data words independently.

(CW-No = 7.1,8.1,9.1,10.1) Due to the combination of codewords (1.1) to (1.4) shown above, as shown in FIG. 4, even when codewords are connected, d, The k-limit can be met. Among the 12-bit codewords, only the codewords satisfying the above conditions (I) and (II) are combined according to (1.1) to (1.4), and the number of codeword sets obtained is calculated by a computer. Using 26
It can be easily confirmed that it is 4.

Therefore, since the number of 8-bit data words is 256, the 12-bit RLL code satisfying d = 2, k = 10 according to the present invention can convert the 8-bit data words without omission.

In "PARAMETERS" of FIG. 4, E and LB are values related to the R block of the first code word W1 of FIG. 3, F is a value of the L block of W2 of FIG. 3, and Y is W2. F ≠
In the case of 1, when W2 is used as the back pattern, Y =
“1”, a value of Y = “0” for a table pattern, S is a parameter effective only when replacing the preceding codeword W1 to satisfy the d, k restriction, and LB = S Choose W1 Further, "-" indicates that it has nothing to do with W1, and "EXAMPLE" in FIG. 4 exemplifies the states of the R block of W1 and the L block of W2 corresponding to the values of the respective parameters.

The connection rules for the code words shown in FIG. 4 are summarized as follows. It is assumed that the code word W0 preceding W1 and the TB of the code word W1 following W0 are already determined.

(I.1) (W2 F = 0) or (W1 E = 0 and W2 F
= 2), W2 is selected and used so that TB of W2 = LB of W1.

(I.2) When (F1 of W1 and F = 2 of W2), T of W2
W2 is selected and used so that LB of B ≠ W1.

(I.3) When (F of W2 is 1 and E of W1 is 0), T of W1
Select W1 so that LB of W1 = TB of W2 without changing B.

(I.4) When (F = 1 of W2 and E = 1 of W1), W1, W2
Both are used as they are.

(I.5) When (F of W2 = 1 and E of W1 = 2), T of W1
W1 is selected and used so that LB of W1 ≠ TB of W2 without changing B.

The above (I.1) corresponds to No. = 1,2,5 to 8,15,16 in FIG. 4, and in this case, LB = TB, so the number of consecutive bits of the same binary value in the connection part is BLEN. Becomes BLEN = r + 1.

Here, when F = 0, since 1 = 1 from the above definition, BLEN = 1 + r, and 1r9, so d = 2
BLEN10 = k, which satisfies the d, k limit.

On the other hand, when E = 0 and F = 2, from the above definition, r = 1,7l
Since it is 9, d <7 BLEN = r + 1 + 1 + 110 = k, which satisfies the d, k restriction.

The above (I.2) corresponds to No. = 13,14,19,20 in FIG. 4, and at this time, LB ≠ TB, and E1 (2
Since r9) and F = 2 (7l9), the d, k restriction is satisfied.

The above (I.3) corresponds to No. = 3,4 in FIG. 4, and at this time, since LB = TB, the above BLEN = l + r, but from the above definition, E = 0 (r = 1), Since F = 1 (2l5), d <3 BLEN7k and the d, k limit is satisfied.

The above (I.4) corresponds to No. = 9 to 12 in Fig. 4, and LB
If ≠ TB (No. 10, 11), E = 1 (2r
5) and F = 1 (2l5), the d, k constraint is satisfied.

On the other hand, when LB = TB (No. 9 and 12), BLEN = r + l, but 4r + l10, so d <4BLEN10 =
k, which satisfies the d, k constraint.

The above (I.5) corresponds to No. = 19,20 in FIG. 4, where LB ≠ TB, and E = 2 (7r
9) and F = 1 (2l5), the d, k restriction is satisfied.

As described above, due to the combination of the codewords of (1.1) to (1.4) and the connection rule of (I.1) to (I.5), d = 2,
Obtain an RLL code that satisfies k = 10.

In addition, the reason why the TB of W1 is not changed in the above connection rules (I.3) and (I.5) is that when the TB of W1 is changed, the codeword W0 preceding W1 or the codeword preceding W0 This is because you have to go up to and control it.

Also, when W1 is changed (I.3), (I.5), W1 E ≠
In 1), the combination of the codewords (1.1),
As can be seen from (1.3), for codewords with E ≠ 1, T
Since the values of B and F are the same and the codewords of LB = 0 and LB = 1 are always combined, the parameter related to the L block of W1 does not change even if W1 is replaced, and therefore the codeword W0 preceding W1 The number of consecutive bits of the same binary value in the connection part of W1 is also 2 or more and 10 or less, which satisfies the d, k limit.

Next, the realizing means of the present invention will be described with reference to FIG. In FIG. 1, a data word holding circuit 1 sequentially holds 8-bit data words sent periodically. The output of the data word holding circuit 1 is input to the code word generation circuit 2 and the code word generation circuit 3. In the code word generation circuit 2,
The code word CW (F, E, 0) with TB = 1 (F = 0,1,2, E =
0,1,2) and the code word CW (1, E, 0) (E = 0,
1, 2) and parameters F, E for the L, R blocks of those codewords. Here, the code word generation circuit 2
Let CWia be the codeword that appears in the output of. On the other hand, in the code word generation circuit 3, the code word CW (F, E, 1) with TB = 1 (F = 0,1,
2, E = 0,2) and TB = 0 codeword CW (1, E, 1) (E = 0,
2) is generated. Here, the code word appearing at the output of the code word generating circuit 2 is CWib. The code words CWia and CWib are both transmitted serially.

The codewords CWia and CWib are codewords combined according to Table 1, and those having the same binary value TB forming the L blocks are selected. Furthermore, when the code word A with TB = 1 and its back pattern A ′ are combined, the code word A
Shall be generated. It should be noted that in Table 1, codewords that are not combined with other codewords are defined to be generated by the codeword generation circuit 2.

The holding circuit 4 and the holding circuit 5 use the R of the preceding code word W1.
Holds the values of parameters E and LB related to blocks. The value of LB may be the value of the last bit of the codeword.

The Y generation circuit 6 generates a value Y for controlling whether W2 is a back pattern according to FIG. 4 (Y = 1: back pattern).

In the output of the exclusive OR (EXOR) gate 7, CWia ^* {= CWia (Y = 0) or the back pattern CWia '(Y = 1)} of CWia appears according to the value of Y, and the EXOR gate is also present. In the output of 7, CWib ^* {= CWib (Y = 0) or CWib back pattern CWib ′ (Y = 1)} appears. After this, the code word CWia
^{The *} is sent to the 12-bit delay circuit 9, and the code word CWib ^* is sent to the 12-bit delay circuit 10.

On the other hand, the holding circuit 11 holds the value of the first bit TB of CWia ^* . The holding circuit 4 holding the output of the holding circuit 11, the parameter F related to the L block of the code word CWia which is the output of the code word generation circuit 2, and the parameters E and LB related to the R block of the preceding code word W1 According to FIG. 4, using the output of the circuit 5, if the output of the 12-bit delay circuit 9 is selected as W1, S = 0, and if the output of the 12-bit delay circuit 10 is selected, the value S is set to S = 1. It is the S generation circuit 12 that generates it.

The switch 13 selects and outputs the output of the 12-bit delay circuit 9 and the output of the 12-bit delay circuit 10 according to the value of S.
As a result, the code word CW _(i-1) is output to the switch 13.
* (= CW _{(i-1) a} * or CW _{(i-1) b} * appears, and the codewords combined according to Table 1 can be connected according to FIG.

As described above, the circuit configuration of FIG. 1 converts an 8-bit code word into a 12-bit data word, and connects the converted 12-bit data words together to generate consecutive bits of the same binary value in a bit string. The number can be limited to 2 or more and 10 or less.

In FIG. 1, code word generation circuits 2 and 3 correspond to the code word generation means, Y generation circuit 6 and EXOR gates 7 and 8 correspond to the first selection means, and 12-bit delay circuits 9 and 10 are provided. Corresponds to the delay means, and the S generation circuit 12 and the switch 13 are the second
It corresponds to the selection means of.

According to the present invention, an 8-bit data word is directly code-converted into a 12-bit code word to obtain an RLL code having performance suitable for high-density recording with Tw = 0.667T and d = 2, k = 10. Realized with a very simple circuit configuration. As a result, in the code conversion of digital data in units of 8 bits, the code word error of one word at the time of decoding does not expand to two words, and the decoding error rate of the data word can be improved as compared with the conventional case. Therefore,
The present invention is particularly effective for a digital VTR or an optical disk that requires high-density recording, and can be realized with an extremely small circuit scale, and the practical effect of the present invention is great.

For convenience of explanation, NRZL recording is assumed, but it goes without saying that it can be easily applied to NRZI recording.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a circuit configuration for implementing the present invention, FIG. 2 is an explanatory diagram showing the structure of code words, FIG. 3 is an explanatory diagram showing connections between code words, and FIG. It is explanatory drawing of the connection rule of words. 2, 3 ... Code word generation circuit (code word generation means), 6 ... Y
Generating circuit, 7,8 ... EXOR gate, 9,10 ... 12 bit delay circuit (delay means), 12 ... S generating circuit, 13 ... Switch.

Claims (1)

[Claims] 1. A code conversion device for converting an 8-bit data word into a 12-bit code word, wherein in a bit string obtained by connecting 12-bit code words of a code conversion output to an 8-bit data word input. , Codeword generation for generating at least one 12-bit codeword for the 8-bit data word input in order to limit the number of consecutive bits of the same binary value to 2 or more and 10 or more and k or less Means, first selecting means for selecting the output of the code word generating means, delay means for delaying the output of the code word selecting means, and second selecting means for selecting the output of the delay means. A code conversion device characterized by the above.