JPS63229921A - Code converter - Google Patents

Abstract

PURPOSE:To prevent an error from being expanded by realizing a means controlling either or both of a preceding code word and a succeeding code word so as to increase the number of code words constituting an RLL code. CONSTITUTION:An output of a data word holding circuit 1 is given to code word generating circuits 2, 3. Holding circuits 4, 5 hold the parameter relating to the block of the preceding code word. An inversion control signal generating circuit 6 generates a value controlling whether or not a code word is taken as an inverted pattern. The code word is fed to 9-bit delay circuits 9, 10 via inversion control circuits 7, 8 and the value of the head bit is stored in a storage circuit 11. A selection circuit 13 selects the output of the 9-bit delay circuits 9, 10 and sends it.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a run length limited device suitable for use in recording digital signals.
ed) relates to a code conversion device for realizing a code.

Conventional technology When recording digital data at high density on magnetic tape or disk, run-length limited codes (
(hereinafter referred to as RLL code) is used. What is RLL code?
A code that limits the number of consecutive bits of the same binary value in a bit string obtained by converting a bit data word to an n-bit code word and connecting the converted n-bit code words to a value greater than or equal to d and less than or equal to d. To tell.

Assuming that the length of one pit of a data word is T, the following three points are known as desired conditions for an RLL code suitable for high-density recording.

(1) The detection window width Tw (=m/n-T) is large (
2) The minimum inversion interval Tmin (=d-Tw) is large. (3) The maximum number of consecutive pits k is small. Detection window width Tw
The larger Tm1n is, the smaller the influence of time axis fluctuations such as peak shifts and peak shifts during the reproduction process on the decoding error rate, and the larger the minimum inversion interval Tm1n is, the smaller the influence of high frequency component cutoff characteristics of the recording/reproducing system. The smaller the maximum number of consecutive bits k is, the easier it is to obtain a self-clock function for extracting clock information from the reproduced signal.

Conventionally, various RLL codes have been developed from the above viewpoint, and Franaszek et al.
.

USP 3,889,899) is one of them62
According to the above definition, the /3 conversion code is d=2, k=9
.

Tw = 0.667T, and a 2-bit data word is
This is a variable length RLL code that switches between converting into a bit code word and converting a 4-bit data word into a θ-bit code word.

Problems to be Solved by the Invention Although it is an excellent RLL code that satisfies the conditions (1) to (3) above in terms of the 2/3 conversion and the 44 conversion, There is. For this reason, when converting the code of digital data represented by 5 bits, for example,
A data word break may span two words of 5-bit, one-word data. In such a case, an error in one code word during decoding propagates (expands) to two words of 5-bit data.

Although RLL codes are used for the purpose of not deteriorating the decoding error rate even when performing high-density recording,
//3 Since the conversion code is a variable length RLL code, decoding errors will be increased. This is a serious problem that must be resolved.

An object of the present invention is to solve the problems of the conventional example, and to achieve d (= 2) and Tw (=0
．． An object of the present invention is to provide a code conversion device that realizes a fixed-length RLL code having a fixed-length RLL code (667T).

Means for Solving the Problems The present invention is a code conversion device that converts a 5-bit data word into a 9-bit code word, and the code words of the code conversion output for the 5-bit data word input are connected to each other. a first code word generating means for generating a 9-bit code word for the 5-bit data word input in order to limit the number of consecutive bits of the same binary value to 2 or more in the pit string obtained by the process; , based on information regarding the immediately preceding codeword and information regarding the output codeword of the first codeword generating means, the first
an inversion control signal generation means for generating a control signal for controlling whether or not to invert the output of the first codeword generation means; a first inversion control means for controlling inversion/non-inversion with respect to the output code word; a first delay means for delaying the output of the first inversion control means; the second to generate a codeword of bits;
a second inversion control means for controlling inversion/non-inversion of the code word output from the second code word generation means based on the output of the inversion control signal generation means;
a second delay means for delaying the output of the second inversion control means; information regarding the code word of the output of the first delay means; and information regarding the code word of the output of the first code word generation means. a selection signal generation means for generating a signal for selecting a code word output from the first delay means and a code word output from the second delay means, based on the output of the selection signal generation means; selection means for selecting a code word output from the first delay means and a code word output from the second delay means; and dividing the 9-bit code word into a 5-bit code word and a 4-bit code word. a temporary decoding means for generating 4 bits for identifying the 5-bit code word divided by the code word dividing means; and 4 bits output from the temporary decoding means and the code word dividing means. A code converting device comprising a final decoding means for inputting a total of 8 bits of the 4-bit code word output from the code word dividing means and decoding a 5-bit data word corresponding to the 9-bit code word input to the code word dividing means. It is.

Function The present invention provides a code word W1 that precedes and a code word W that follows Wl.
2, or both. As a result, the number of code words constituting an RLL code has increased compared to before, and it is possible to directly convert a 5-bit data word into a 9-bit code word, which was previously impossible, to create an RLL code that satisfies the restriction of d = 2. is obtained (Tw=0,667T)
, eliminating error expansion.

Example Next, the present invention will be described in detail using k=12 as an example.

Note that although k=12 is larger than s of the conventional 2/3 conversion code, it is a value that allows a sufficient self-clock function to be obtained and does not cause any practical problems. For convenience of explanation, parameters representing the characteristics of code words as shown in FIG. 2 are defined in order to classify code words used in the present invention. L block: Starting end of a code word with consecutive 1 bits of the same binary value TB R block 2r pit End of a code word with consecutive same binary values LB B block: b (=9-1-r ) Intermediate part of bit code word Code words used in the present invention are limited to those that satisfy the following conditions.

(I) 1≦1≦9.1≦r≦6 (I[) In B block, ω that completely satisfies the restriction d) means that in B block, 0 and 1, which are more than d bits and less than d bits, alternate. (b=o
except for). Furthermore, with respect to 1 and r, the following parameters F,
Introduce E.

F=O (1=1), F=1 (2≦1≦6).

F=2 (1≧7), E=o (r=1).

E=1 (2≦r≦6) The four parameters (TB, F.

The connection between code words is controlled based on the first code word W1 shown in FIG.
With respect to the connection between the code word W2 and the second code word W2, this means that the connection part between the R block of the code word W1 and the L block of the code word W2 also satisfies the restriction on d. Hereinafter, the rules regarding the connection between code words will be referred to as a connection part.

Chapter 1 Table Table 1 shows the four parameters (TB, F.

3 shows the code word combination rules in the present invention, which are defined based on E, LB). In Table 1, CW-,c is a combination number of code words and an identification number of the code words forming the combination, and the code words forming one combination are associated with the same data word.

TB, F, E, and LB in Table 1 are parameters related to code words, and the example shows an example of a code word that can be represented by the parameters. Next, the code word combination rules in Table 1 will be explained in detail.

Note that a code word in which all 1's in code word A are replaced with 0 and all 0's are replaced with 1 is called a back pattern of code word A, and is expressed as A'.

(1) F〆1. E=O, TB=1. LB=1゜LB=1
The O code word CW (F, o, 1) is its back pattern CW (
F,o,1)' and CW(F.

o, 1) and F, E, TBO values are equal, LB=.

The code word CW (F, E, o) and its back pattern cW (
Combine with F, O, O)'.

(CW-sink=1) (2) F〆1, E:1, TB=1 code word CW(F
, 1. X) is its back pattern CW (F.

1. Combine with X)'. In addition, X represents both ◯ and 1.

(CW'-4=2, 3, 10) (33F=1, E=O, TB=1, LB=1(7
) Code word CW (1, o, 1) has the same values of F, E, TB as CW (1, o, 1), and the code word CW (1
,0,0).

(CW'-ya=4. e; ) (4) F=1+ E=1o sign 1cW(1,1,X
) and its back pattern CW(1,1,X)' are not combined with other code words, but are made to correspond to data words alone.

(CW-4 = 6.0, 8.9) Table 2 Table 3.1 Table 3.2 By combining the code words (1) to (4) shown above, as shown in Table 2. Even when code words are connected to d, the restriction on d can always be satisfied.

Among the 9-bit codewords, only the codewords that satisfy the condition (1) above are combined according to (1, 1) (1, 4), and the number of codeword pairs obtained is the third As shown in the table, it is 66. Note that the combinations in Table 3 are just examples, and any combination may be used as long as the code word combination rules in notes (1) to (4) are followed.

Since the number of data words that can be expressed with 5 bits is 64,
d=2 in the present invention. A 9-bit RLL code that satisfies =12 can convert all 6-bit data words. Next, means for realizing the present invention will be explained using FIG. 1. In FIG. 1, a data word holding circuit 1 sequentially holds 5-bit data words sent periodically. The output of the data word holding circuit 1 is input to the code word generation circuit 2 and the code word generation circuit 3. In the code word generation circuit 2,
The code word CW (F, E, 0) (F=
0.1.2. E=0.1) and TB=.

The codeword CW (1, E, o) (E=o, 1), the codewords thereof, and the parameters F and E regarding the R block are generated. Here, the code word appearing in the output of the code word generation circuit 2 is assumed to be CWia. On the other hand, in the code word generation circuit 3, the code word CW (F,○$1
) (F=0.112) and the code word CW(1
, 0, 1). Here, the code word appearing in the output of the code word generation circuit 2 is assumed to be CW i b. Note that both code words CW i a and CWib are transmitted serially. Codewords CW f a and CWib are codewords combined according to Table 1, and the binary values TB constituting their L blocks are selected to be equal to each other. Further TB=
When the code word A, which is 1, and its back pattern A' are combined, the code word A is generated.

Note that in Table 1, codewords that are not combined with other codewords are determined to be generated by the codeword generation circuit 2.

The holding circuit 4 and the holding circuit 6 hold the values of parameters E and LB regarding the R block of the preceding code word W1. Note that the value of LB may be the value of the last bit of the code word.

The inversion control signal generation circuit 6 generates a value Y for controlling whether or not to make -y2 a reverse pattern according to Table 2 (Y=1
: Back pattern).

The output of the inversion control circuit 7 has CW'i depending on the value of Y.
a” (=CWia (V=O), or CWia
The back putter /cWia' (V=1)) appears, and CWi b'' (=CWi
b (V=O) or CWib c7) Back pattern cw
ib′(■=1)) appears. After this, the code word CWi
♂ is sent to a 9-bit delay circuit 9, and the code word CWib'' is sent to a 9-bit delay circuit 10, respectively.

On the other hand, the holding circuit 11 holds the value of the leading pin ()TB of CWi♂. The output of the holding circuit 11, the parameter F regarding the L block of the code word CWia which is the output of the code word generation circuit 2, and the parameter E regarding the R block of the preceding code word W1.

Using the outputs of the holding circuit 4 and holding circuit 6 that hold LB, and selecting the output of the 9-bit delay circuit 9 as wl according to Table 2, S=o, and the output of the 9-bit delay circuit 10. If selected, the selection signal generation circuit 12 generates a value S that makes S=1.

The selection circuit 13 selects and transmits the output of the 9-bit delay circuit 9 and the output of the 9-bit delay circuit 1o according to the value of S. As a result, the output of the selection circuit 13 includes the code word CW (
i-1)" (:CW(t,1)am, j or CW(i-1)b appear, and the codewords combined according to Table 1 can be connected according to Table 2.

As shown above, an 8-bit code word is converted into a 9-bit data word using the circuit configuration shown in FIG.
The number of consecutive pits of the same binary value in a bit string generated by connecting data words of bits can be limited to 2 or more and 12 or less.

Next, a decoding circuit that decodes a 5-bit data word from a 9-bit code word will be described.

In conventional decoding methods, the 9 bits to be decoded must be directly decoded into a 5-bit data word. ROM this decryption
(Read ONLY Memory), the capacity required for the ROM is 2×6=3 kbits.

On the other hand, the capacity of the ROM required for the decoding circuit used in the present invention can be reduced to approximately 1.6 kbits. Hereinafter, the decoding circuit of the present invention will be explained in detail using FIG. 4.

Table 4 In FIG. 4, first, a 9-bit code word appears in the output of the holding circuit 15 that holds the output of the serial-parallel conversion circuit 14 for converting a bit string into parallel data in code word units. .

Next, the 9 bits to be decoded are divided into two bit strings of 5 bits and 4 bits. At this time, there are 16 bit patterns for the first 5 bits of the code word in Table 1 as shown in Table 4, and each bit pattern can be identified by 4 bits.

The temporary decoding circuit 16 outputs a 4-bit identification number corresponding to the input of the first 5 bits of the 9-bit code word.

4 bits from temporary decoding circuit 16 and lower 4 bits of holding circuit 16
The total 8-bit value is input to the final decoding circuit 17.

Since these 8 bits are the identification number of the 9-bit code word to be decoded, the final decoding circuit 17 may be set to decode the e-bit data word corresponding to the input 9 bits.

The capacity of the ROM required for the above decoding is as follows. First, (2 x 4) = 128 bits are used for the temporary reconnaissance code, and 2 x 6 = 1.5 kbits are used for the final decoding.

Therefore, the ROM capacity required for decoding is approximately 1600b.
ITS, which is about 1/2 of the conventional value.

Effects of the Invention The present invention directly converts a 5-bit data word into a 9-bit code word, and creates an RLL code with Tw=0.667T and d=2, which has performance suitable for high-density recording. This was achieved with a simple circuit configuration. As a result, with regard to code conversion of digital data in units of 5 bits, a code word error of one word during decoding will not expand to two words, and the decoding error rate of data words will be increased compared to the conventional method. It can be improved.

Furthermore, by using a two-stage decoding method that combines preliminary decoding and final decoding, the capacity of the ROM required for decoding can be reduced to about 1/2 compared to conventional decoding methods.

As described above, the present invention not only realizes an RLL code with excellent recording and reproducing characteristics, but also has the excellent feature of being extremely easy to put into practical use. Therefore, the present invention is particularly effective for digital VTRs, optical discs, etc. that require high-density recording, and in addition to being able to be realized with an extremely small circuit scale, the present invention has great practical effects.

For convenience of explanation, the explanation was based on NRZL records,
Needless to say, this method can be easily applied to NRZI records as well.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a circuit configuration for realizing the present invention, Figure 2 is an explanatory diagram showing the structure of code words, Figure 3 is an explanatory diagram showing connections between code words, and Figure 4 is decoding. It is a block diagram of a circuit. 1... Data word holding circuit, 2, 3...
code word generation circuit, 4,5.11...holding circuit,
6... Inversion control signal generation circuit, 7, 8...
...Inversion control circuit, 9゜1o...Delay circuit, 1
2... Selection signal generation circuit, 13... Selection circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4

Claims (1)

[Claims] A code conversion device that converts a 6-bit data word into a 9-bit code word, wherein the bit string obtained by connecting the code words of the code conversion output for the 6-bit data word input is a sequence of the same binary value. In order to limit the number of pits to 2 or more, first code word generation means generates a 9-bit code word for the 6-bit data word input, and information regarding the immediately preceding code word and the first code. an inversion control signal generation means for generating a control signal for controlling whether or not to invert the output of the first codeword generation means based on information regarding the codeword output from the word generation means; and the inversion control. a first control unit that controls inversion/non-inversion of the code word output from the first code word generation means based on the output of the signal generation means;
an inversion control means, a first delay means for delaying the output of the first inversion control means, and a second code word generation means for generating a 9-bit code word in response to the 6-bit data word input. and a second inversion control means for controlling inversion/non-inversion of the code word output from the second code word generation means based on the output of the inversion control signal generation means; a second delay means for delaying the output; and the first delay means based on information regarding the code word output from the first delay means and information regarding the code word output from the first code word generation means. a selection signal generation means for generating a signal for selecting a code word output from the second delay means and a code word output from the second delay means; and an output of the first delay means based on the output of the selection signal generation means. and the code word of the second
selecting means for selecting a code word output from the delay means; code word dividing means for dividing the 9-bit code word into a 5-bit code word and a 4-bit code word; a temporary decoding means for generating 4 bits for identifying a 5-bit code word, and a total of 8 bits of the output 4 bits of the temporary decoding means and the 4 bit code word output from the code word dividing means as input. , a code conversion device comprising final decoding means for decoding a 6-bit data word corresponding to a 9-bit code word input to the code word dividing means.