JPH0422060B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to an information conversion method suitable for use in PCM recording of audio signals and the like. BACKGROUND TECHNOLOGY AND PROBLEMS For example, it has been proposed to convert audio signals into PCM and magnetically record them using a rotating head. When recording signals in such devices, modulation generally called NRZI is used. This is to invert the signal when it is "1" in the data signal, and not to invert it when it is "0". By the way, when recording such a signal, if a large amount of low-frequency components are included, stability during reproduction deteriorates. On the other hand, if "0" continues in the above-mentioned NRZI, the modulation signal will not be inverted during that time, and the frequency will drop. Therefore, the PCM information is broken down into an arbitrary number of bits, and each bit is converted into a larger number of bits to prevent a large number of consecutive "0"s. In addition, when trying to perform the above-mentioned recording using a small device such as a portable device, it is necessary to downsize the rotating head,
Due to the narrowing of the recording track, there are problems such as a poor S/N ratio of the reproduced output and a narrow recording band. For example, for S/N, the detection window width (Tw) during demodulation and the minimum inversion width (Tmin)
It is desirable that the ratio is as small as, for example, 2 times or less. Therefore, for example, a conversion method called the Gabor code has been proposed. The Gabor code converts 2 bits (B ₁ , B ₂ ) of information into 3 bits (P ₁ , P ₂ , P ₃ ), and the conversion formula is P ₁ = _3p + B ₁ + ₂・B _1f P ₂ =P _3p・₁ +B ₂ P ₃ = _3p +B ₁ +B _2However , p in the saphix is the previously converted information, f is the next converted information, and the demodulation formula is B ₁ = _3p・P _1p +P _3p・P ₁・P ₃ B ₂ =P ₂・P ₃ is given. In this Gabor code, Tw=0.67T,
Tmin = 0.67T, Tmax (maximum inversion width) = 1.33T (where T is the time or wavelength equivalent to 1 bit of modulated data), where the ratio of Tw and Tmin is 1.
It's double. Furthermore, a conversion method called 4/5 conversion has also been proposed. 4/5 conversion method is 4 bits (B ₁ , B ₂ , B ₃ , B ₄ )
This _{is to convert the} information _of In other words, within a combination of 5 bits, there are no consecutive 0s at the beginning or end, and there are no 0s between them.
There are 17 consecutive numbers of 2 or less as shown in Figure 1. Therefore, the 16 ways of the 4-bit modulated data (0000) to (1111) are
Conversion is performed by making a one-to-one correspondence with any 16 of the streets. In this way, conversion can be performed such that the number of "0"s between "1"s is always 2 or less. In this 4/5 conversion method, Tw=0.8T, Tmin
= 0.8T, Tmax = 2.4T, where Tw and
The ratio of Tmin is 1. However, in these methods, a DC component exists in the signal after NRZI conversion. If there is a DC component in the modulated signal, that is, the recorded signal, for example, the original signal as shown in FIG. 1A will be reproduced as shown in FIG. 1B. In reality, as shown in Figure 1C, the DC component is offset and reproduced to 0, and the output signal becomes a signal whose time axis has been varied as shown in Figure 1D, resulting in a faithful signal. Digital waveform reproduction is not possible. For this reason, since the frequency and the like are determined taking these into consideration, there have been problems such as the inability to increase the recording density. In response to this, the applicant of the present application previously proposed a method that performs conversion without a DC component based on 4/6 conversion. That is, when converting 4-bit information (B ₁ , B ₂ , B ₃ , B ₄ ) to 6-bit information (P ₁ , P ₂ , P ₃ , P ₄ , P ₅ , P ₆ ), 4-bit information ( There are ²⁴ = 16 possible forms of the information B ₁ to B ₄ ). On the other hand, for 6 bits (P ₁ to P ₆ ), in order to remove the DC component, first, if 3 bits out of 6 bits are positive (1) and 3 bits are negative (0) in the signal after NRZI modulation, then good. Note that in order to set Tmax/Tmin=3, the condition is that the number of consecutive "0"s in the NRZI representation is 2 or less, that is, the number of consecutive "0"s in the modulated signal is 3 or less at the same level. Considering these conditions, we further consider that the number of first or last “0” is 0 or 1 in NRZI representation.
The combinations for each case are as shown in Table 1 below.

[Table] From Table 1, we can see that even in the connection between 6-bit patterns, the number of consecutive “0”s is two or less, A ₁ where the first bit is “1”,
10 combinations of A ₁ ′, A ₁ ″, then 12 combinations of A ₁ , B ₁ , C ₁ where the last bit is “1”, and then 1 in which both the number of first and last “0” is 1 less than or equal to A ₁ ,
This is a case of 15 combinations of A ₁ ′, B ₁ , and B ₁ ′.
However, in any of these cases, the number of combinations is less than the number of 4-bit 16 combinations. Therefore, combinations that cannot be used originally, such as A ₁ ,
When using A ₁ ′, A ₁ ′, use combinations such as B ₁ , B ₁ ′, etc., and reduce the number of consecutive “0”s to 2 or less by converting some of them to 8/12. proposed a method. However, in this method, the constraint bit length required for conversion is 8 bits, and for inverse conversion it is 12 bits, which is extremely long, resulting in an extremely large device and the propagation of errors, which is a practical problem. OBJECTS OF THE INVENTION In view of these points, the present invention proposes an information conversion method that does not have a DC component and has a short constraint bit length. Summary of the Invention In the present invention, when converting 4-bit information into 6-bit information, the 6-bit information is converted into NRZI
A first combination in which the same level continues for 3 bits or less in the modulated signal, and the accumulation of DC in the 6 bits is 0, and a second combination in which the accumulation of DC is 2. Then, the above 4-bit information corresponds one-to-one with the combination selected under the above conditions, and when the second combination is used, the sign of the DC accumulation is stored, and then An information conversion method that converts the first bit of the next second combination so that when the second combination is used, the accumulation of the DC has a sign opposite to that stored in the memory, According to , it is possible to remove the DC component after NRZI modulation, and
The restraint bit length is also short. Example In the 4/6 conversion method, combinations other than DC component 0 will be considered. In that case, the combinations of DC accumulation amounts of +2 and -2 are as shown in Tables 2 and 3 below.

【table】

[Table] Here, regarding the accumulated amount of DC, for example, as shown in Figure 2, the last of the previous combination is negative (0).Therefore, the last of the previous combination is positive (1).
If it ends with , the positive and negative signs are reversed. Further, for example, for a combination in which the leading bit is "0", if this leading bit is converted to "1", the sign of the accumulated amount of DC is reversed as shown in FIG. So, for example, when using A ₁ , A ₁ ′, B ₁ , and B ₁ ′ in Table 1, there are two ways, B ₂ and B ₂ ′ in Table 2, and two ways in Table 3.
Using the three combinations of B ₃ and B ₃ ', 16 4-bit combinations are created from a total of 20 combinations, including the 15 first combinations without DC component mentioned above and 5 second combinations. and have a one-to-one correspondence. Then, each time the second combination appears, the leading bit is converted so that the accumulated amount of DC is alternately positive and negative. In this case, even if the first bit "0" is converted to "1", it will only result in the opposite combination of DC accumulation amount A in Tables 2 and 3, and there is no risk of confusion with other combinations. do not have. Here, the combination of A ₁ , A ₁ ′, B ₁ , B ₁ ′ in Table 1 is C ₀ ,
The combination of B ₂ and B ₂ ' in Table 2 is C ₊₂ , the combination of B ₃ and B ₃ ' in Table 3 is C _-2 , and the first bit of C ₊₂ is "1".
The amount of DC accumulated after being converted to -2 is
The first bit of C ₊ ′ ₂ and C _-2 is converted to “1” and becomes +
Let C _-2 ' be the DC accumulation amount of 2. In this case, as shown in Figure 4, when the second combination appears, the number of inversions (the number of "1"s) is counted from the second bit, and The combination is C ₊₂ (or C ₊₂ ′) and C ₊₂ ,
Or, if they have the same sign, such as C _-2 (or C _-2 ′) and C _-2 ′, if the number of inversions is an even number, the first bit (arrow) is is converted to "1", and if it is an odd number, it remains "0" as shown in B. In addition, if the previous second combination and the second combination have different signs, the first bit is left as "0" as shown in C when the number of inversions is an even number, and as shown in D when the number of inversions is an odd number. Convert the first bit to "1". That is, the conversion shown in Table 4 below is performed.

[Table] Even if this causes an accumulation of DC of ±2, this will be canceled out by the next second combination, and the DC component will be 0 in any series of combinations. Furthermore, FIG. 5 shows an example of an apparatus for performing conversion according to the above-described method. In the figure, 1 is the input terminal, 2
is a 4-bit shift register for input, 3 is a conversion logic, and 4 is a 6-bit shift register for output. The information supplied to the input terminal 1 is 4-bit information (B ₁ to _{B 4} ) and is supplied to the conversion logic 3. This conversion logic 3 performs the above-mentioned one-to-one conversion, and the converted 6-bit (P ₁ to _{P 6} ) information is supplied to the shift register 4. Furthermore, the number of inversions of the signal after conversion and the amount of accumulated DC are detected. Here, since the number of inversions and the amount of DC accumulation are known in advance for each combination, information on the number of inversions and the amount of DC accumulation can be obtained at the same time, for example, from the read-only memory constituting the conversion logic 3. For example, when a second combination appears, the output Q is taken out as shown in Table 5, depending on the sign of the DC accumulation amount of that combination and the number of inversions after the second bit.

[Table] This output Q is supplied to a latch circuit 8, and this latch output Q' is supplied to a conversion logic 3. Further, the timing of every 4 bits of information supplied to the input terminal 1 is detected by the detection circuit 9, and this timing signal is supplied to the load terminal of the shift register 4 and the latch terminal of the latch circuit 8. Furthermore, when the first combination appears, the following table 6 is shown according to the number of inversions and the input Q' from the latch circuit 8.
The output Q is taken out as follows.

[Table] Then, when converting to the next second combination, the first bit is converted as shown in Table 7 according to the DC storage amount of that combination and the input Q'.

[Table] At that time, information on the number of inversions and the amount of DC accumulation of the second combination outputted is outputted and latched to Q according to the above-mentioned Table 5. Furthermore, a clock signal having a frequency 3/2 times that of the input signal clock is supplied from the clock terminal 5 to the shift register 4, and the above-mentioned 6 bits are sequentially read out. This signal is supplied to the JK flip-flop 6, the clock signal from the terminal 5 is supplied to the flip-flop 6, and the NRZI modulated signal is taken out at the output terminal 7. Further, FIG. 6 shows an example of a device for demodulation, in which a signal from an input terminal 11 is supplied to a 6-bit shift register 13 through an NRZI demodulation circuit 12,
Information (P ₁ to _{P 6} ) from the shift register 13 is supplied to the conversion logic 14. Demodulation is then performed by the above-described one-to-one inverse conversion, and the demodulated information (B ₁ to B4) is supplied to the shift register 15 and taken out to the output terminal 16. Note that when 6 bits of the above-mentioned second combination are supplied, the first bit is ignored and the inverse conversion is performed. Conversion and demodulation can be performed in this way. And in this method, Tw=Tmin=
0.667T, Tmax=2T. The above-mentioned Gabor code has the disadvantage of an increase in low-frequency components due to the widening of Tmax, but this disadvantage is offset by the absence of DC components in this method, resulting in better recording. Can be played. Also, compared to the 4/5 conversion method mentioned above, the recording density is slightly lower, but since there is no DC component in this method, there is no time axis fluctuation of the reproduced signal as described above, and recording and reproduction at higher frequencies is possible. Therefore, the recording density can be increased. Further, the constraint bit length does not become long unlike when the above-mentioned 8/12 conversion is used together. Effects of the Invention According to the present invention, the DC component after NRZI modulation can be removed, and the constraint bit length can also be shortened.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the conventional system, Figures 2 to 4 are diagrams for explaining the present invention, and Figures 5 and 6 are block diagrams of devices used for conversion and demodulation, respectively. be. 1 is an input terminal, 2 and 4 are shift registers, 3 is a conversion logic, 5 is a clock terminal, 6 is a flip-flop, 7 is an output terminal, 8 is a latch circuit, and 9 is a timing circuit.

Claims (1)

[Claims] 1. When converting 4-bit information to 6-bit information, the above 6-bit information is used so that the number of successive bits of the same level is 3 or less in the signal after NRZI modulation, and the 6-bit information is A first combination in which the DC accumulation is 0, and a second combination in which the DC accumulation is 2, and the 4-bit information is in a one-to-one correspondence with the combination selected under the above conditions, and the above-mentioned When the second combination is used, the positive or negative sign of the DC accumulation is memorized, and the next time the second combination is used, the DC accumulation has a sign opposite to that stored. An information conversion method in which the first bit of the second combination described above is converted.