JPS634270B2 - - Google Patents

Description

[Detailed description of the invention]

This invention provides a binary data encoding method for converting an original binary data sequence into a binary code sequence suitable for recording when recording binary data on a recording medium such as a magnetic tape or a magnetic disk. Regarding. Conventionally, when recording binary data on a recording medium such as a magnetic tape or a magnetic disk,
Various encoding methods have been proposed and put into practical use to improve recording density. Figure 1 is an explanatory diagram of an example of a conventional encoding method.
FIG. 1a shows an example of the bit pattern of the original binary data sequence, where the digits 0 and 1 represent the logic ``0'' and ``1'' bits, and T ₀ represents the bit interval.
Figures b and d are examples of conventional encoding methods; figure b is called the MFM method (Mcdified FM method), and figure d is the 3PM method (3Position method).
Modulation). As examples of models to which each method is applied, the MFM method is used in the magnetic disk drives 3330, 3340, 3350, etc. manufactured by IBM, and the 3PM method is used in the magnetic disk device 8434 manufactured by Unidoc. In the MFM method, the algorithm of each method converts original data "1" and "0" into "01" and "X0", respectively. However, "X" is the complement logic (1→
0, 0 → 1). Furthermore, as shown in Table 1, the 3PM algorithm separates the original data into 3-bit units and converts them into 6-bit codes.

[Table] In the example of the code system converted by each encoding method, the recording current is created so that the signal causes magnetic reversal at the "1" bit and does not cause the magnetic reversal at the "0" bit. and recorded on the recording medium. 1c and 1e are the recording current waveforms (MRZI signals) of code sequences encoded by the MFM method (b) and the 3PM method (d). In general, when recording on magnetic media, (a) As the magnetization reversal interval (recording wavelength) becomes shorter,
Magnetic transitions caused by magnetization reversal before and after each interfere with each other, causing errors when decoding the reproduced signal. (b) If the demodulation phase margin (TW) (described later) during reproduction is small with respect to the recording wavelength, the above error is likely to occur. (c) If the recording wavelength is larger than the period of the demodulation clock signal created from the reproduced signal, the above clock cannot be accurately created from the reproduced signal, making it more likely that the above error will occur. (d) When the ratio between the maximum value and the minimum value of the magnetization reversal interval increases, waveform interference (referred to as pattern peak shift) of the reproduced signal increases, making it easier to cause the same error as described above. For this reason, in general encoding methods, the above
The following variables are given as parameters indicating the ability including the four terms (a), (b), (c), and (d). Now, in a certain encoding system, an m-bit binary data sequence is converted to an n (n≧m)-bit binary code sequence,
If the minimum value of the number of code ``0'' between an arbitrarily selected code ``1'' and the next code ``1'' from the code series after conversion is d, and the maximum value is k, then Tmin( Minimum magnetization reversal interval) = m/n (d+1) To ………(1) Tmax (maximum magnetization reversal interval) = m/n (k+1) To ………(2) CLK (demodulation clock period) = m/ nTo (3) Tw (demodulation phase margin) = m/nTo (4) However, To is given by the original data period. Therefore, from the above explanation, it is desirable that the values of equations (1) and (4) be larger (from the above explanations (a) and (b)), and the demodulation clock period ((3) (formula), the ratio of the maximum magnetization reversal interval (formula (5)), and
It is desirable that the ratio of the maximum and minimum magnetization reversal intervals (formula (6)) be smaller. Tmax/CLK={m/n(k+1)To/m/nTo}=(k
+ 1) ………(5) Tmax/Tmin={m/n(k+1)To/m/n(d+1)To}=k+1/d+1……(6) The above parameters are encoded by the above MFM and 3PM encoding Table 2 shows the encoding method and the encoding method according to the present invention.

[Table] As shown in Table 2, the encoding method according to the present invention is superior to the MFM method in terms of the minimum magnetization reversal interval.
The ability to create a demodulation clock from the reproduced signal (maximum magnetization reversal period/demodulation clock period) and the waveform non-interference ability of the reproduced waveform (maximum magnetization reversal interval/minimum magnetization reversal interval) are superior to the 3PM method. . The present invention will be explained in detail below. Tables 3 and 4 are specific examples of conversion algorithms for the encoding method of the present invention. The conversion algorithm first separates the original data into 2-bit units, and then stores the separated 2-bit data in Table 3 or 4.
Convert to 4-bit code according to the rules in the table. Observing the code string converted by the above conversion algorithm, the parameter m/n=2/4=0.5
Therefore, Tw=0.5To.

[Table] However, A to D; four types of patterns that can be constructed from 2-bit patterns are shown as A, B, C, and D. for example

[Table] En: Data n bits before the 2-bit data to be converted in the original data string Ln: Data n bits after the 2-bit data to be converted in the original data string Y: Y code in the converted code string Complement logic of logical sum of previous 2 bits

[Table] ↑
↑
Original data column Conversion data

【table】

[Table] However, the meanings of A to D; En; Ln; Y are the same as in Table 3. Also, as a code pattern that gives d and k,

【table】

Conversion code: "0010""0100""0000"
”, “0100”, etc., and k = 7. Therefore, it is given by d = 2 and k = 7, and it is understood that Table 2 is satisfied as a parameter capability. Next, regarding the algorithm for performing the conversion shown in Table 3, the regularity of the conversion will be considered. (Table 4 is a partially modified conversion of Table 3, and is basically the same as Table 3.) The regularity is that first, the original data is separated into two bits, and then Convert according to the conversion algorithm table in Table 5.

[Table] However, Y: Complement logic of the logical sum of the two bits immediately before the converted code string

[Table] What can be understood from the basic conversion table algorithm in Table 5 is that in conversions excluding the original data pattern “10” “00”, d=2,
It can be seen that k=7 is satisfied. For this reason, “10”
If the "00" pattern occurs, as shown in Tables 3 and 4, by using a conversion method that is a modified version of the basic conversion algorithm in Table 5, in all pattern conversions, d=2,
It is made to satisfy k=7. FIG. 2 is a block diagram of a specific example of an encoding circuit implementing the encoding method according to the present invention, and FIG. 3 is a timing chart thereof. In FIG. 2, original data is input to input terminal 1. In FIG.
In addition, a clock twice the original data clock (Fig. 3b) is input to input terminal 2, and the signal is divided into 1/2 and 1/4 by 1/2 frequency dividers 4 and 5. (3rd
Figure c and d). Input data is input by shift register (serial 1N, parallel OUT) 6.
Each is delayed by 1 bit, and the data output Q ₉
~Q is output to ₀ . The _Q4 signal at this time is shown in Figure 3a.
shall be. Data output Q ₉ ~ _{Q 0} is gate circuit 30 ~
ROM (Read On Memory, for example, TI's
SN74S471N, etc.) input terminals a ₀ to a ₇ ,
Sign-converted output signals are obtained at output terminals D ₀ to D ₃ .

[Table] However, A ₀ = Q ₀ × ₁ A ₁ = Q ₂ , A ₂ = Q ₃ , A ₃ = Q ₄ , A ₄ = Q ₅ , A ₅ =
Q ₆ , A ₆ = Q ₇ , A ₇ = Q ₈ + Q ₉ Q ₀ = Q ₉ ; Output signal of shift register 6 The logic in the shaded area is arbitrary. By this operation, the original data pattern ( 11010001) is converted to the code pattern (1000001001000010) shown in FIG. 3e. Next, a block diagram of a specific example for realizing decoding of a signal encoded by the present invention is shown in FIG. 4, and a timing chart for explaining the same is shown in FIG. 5.
First, a converted code string f (=e) is input to the input terminal 10, and a demodulating clock g generated from the code string f shown in FIG.
Enter 1. Next, as in the case of encoding, the clock g is divided into 1/2 and 1/4 by the 1/2 frequency dividers 17 and 18 (Fig. 5 i and j), and the input signal f is shifted. The signal is delayed one bit at a time by the register (serial 1N parallel OUT) 13 and output to the parallel OUT terminals Q ₁₂ to _{Q 0} (output terminals with a large amount of delay are set to Q ₀ or less Q ₁ to Q ₁₂ (delay amount small)). Suppose now that the signal f shown in FIG. 5f is being output as the signal at the _Q6 terminal. On the other hand, the signals from the Q ₀ terminal to the Q ₃ terminal are turned into a logical sum signal by an OR gate 15, and are input to an input address A ₀ of a ROM 16 (TI SN74S471, etc.). Also, the signals of Q ₄ to _{Q 9} terminals are similarly input to addresses A ₁ to _{A 6} , and Q ₁₀ to
The _Q12 terminal output is input to the address _A7 as a logical sum signal by the OR gate 14. The ROM 16 has a conversion algorithm for decoding the encoding method according to the present invention, and the conversion algorithm is shown in Table 7.

【table】

[Table] However, A ₀ = Q ₀ + Q ₁ + Q ₂ + Q ₃ , A ₁ = Q ₄ , A ₂ = Q ₅ ,
A ₃ = Q ₆ A ₄ = Q ₇ , A ₅ = Q ₈ , A ₆ = Q ₉ , A ₇ = Q ₁₀ + Q ₁₁
+Q ₁₂ The logic in the shaded part is arbitrary The decoding algorithm is based on the converted code sequence,
The 4-bit code for decoding (specified by addresses A ₇ to _{A 3} ) is converted into the preceding and following code patterns (addresses A ₀ ,
Specified by A ₁ , A ₂ , A ₇ . ), subject to the terms of
It has an algorithm for decoding to 2-bit original data. The decoding pattern is output to the D ₀ and D ₁ terminals. This demodulation ROM algorithm uses three specific address patterns (“A ₂ to _{A 5 ”} = “ ₀₀₀₀ ” and "0100" and "0001")
Only when this happens, the output pattern is changed and demodulated using the algorithm of the code pattern (specified by A ₀ or A ₁ , A ₆ ) within 3 bits before and after. The decoded output signal becomes the preset input of the shift register (parallel IN, serial OUT) 19. On the other hand, the frequency dividers 17 and 18 generate a 4-bit code for decoding using a synchronization signal h (inputted to the input terminal 12, h in FIG. 5) obtained by detecting a synchronization pattern within the conversion code series. is synchronized, and a frequency divider output signal (FIG. 5j) is generated. This signal j causes shift register 1
9 latches the preset input (signals at input terminals H and G), and outputs it to output terminal 20 as demodulated serial data k using the output signal of frequency divider 17 (which serves as a clock for signal demodulation data). be done. If this situation is explained using the time chart of FIG. 5, it will be understood that the (1000001001000010) pattern of the input code f is decoded to (11010001) by the decoded data k. As mentioned above, as shown in Table 2, the encoding method of the present invention has superior ability as a high-density magnetic recording method compared to other conventional modulation methods, and the structure of the leadware is also very good. Its practical value is
Very large. This invention separates a binary data string into every 2 bits, and converts the separated 2-bit data pattern into 4 bits.
When converting into a bit pattern, by performing unique conversion according to patterns within 6 bits before and after the separated 2-bit pattern, any code "1" in the converted coded string can be converted.
It is possible to construct a coded sequence in which there are two or more and seven or less codes "0" between the code "1" that appears next, and to reduce the occurrence of errors during decoding. Can be done.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the conventional MFM method and 3PM encoding method, FIG. 2 is a block diagram of an embodiment to which the encoding method according to the present invention is applied, and FIG. 3 is a timing diagram thereof. FIG. 4 is a block diagram of an embodiment of the decoding method according to the present invention, and FIG. 5 is a timing diagram thereof. In the figure, 2 and 11 are clock input terminals;
1, 10 are data input terminals, 3, 12 are synchronization signal input terminals, 6, 8, 13, 19 are shift registers, 4, 5, 17, 18 are 1/2 frequency dividers, 7, 16
is ROM, 9, 20 are data output terminals, 21 is clock output terminal, 14, 15, 30, 31, 32
is a logic gate. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. When separating a binary data string into every 2 bits and converting the pattern of the separated 2-bit data into a code consisting of 4 bits, Detects the data pattern of the 4 bits before and after, and uses the detected signal to
Bit data is converted into a 4-bit code, and between any code "1" in the converted code string and the next code "1", two or more and seven or less codes "0" are added. 1. A binary data encoding method characterized in that the algorithm for converting 2-bit data into a 4-bit code is based on the algorithm shown in the S1 conversion table below. [Table] [Table] However, A to D: Four types of patterns consisting of 2-bit patterns are shown as A, B, C, and D. Y: Complement logic of the logical sum of the 2-bit code immediately before code "Y" in the converted code string [Table] (3) En: Data n bits before the 2-bit data to be converted in the original data string Bit Ln: Data bit 2 after n bits of the 2-bit data to be converted in the original data string. The binary data string is separated every 2 bits, and the pattern of the separated 2-bit data is composed of 4 bits. When converting into a code, detect the pattern of the preceding 6 bits and subsequent 4 bits of data that follow the 2-bit data, and use the detected signal to convert the 2-bit data into a 4-bit code. and between any code "1" in the converted code string and the next code "1", two or more,
A code for binary data, characterized in that the algorithm for converting 2-bit data into a 4-bit code is based on the algorithm shown in the S2 conversion table below, forming a code string in which there are seven or less code "0"s. method. [Table] However, A to D; four types of patterns consisting of 2-bit patterns are shown as A, B, C, and D. Y: Complement logic of the logical sum of the 2-bit code immediately before code "Y" in the converted code string [Table] (3) En: Data n bits before the 2-bit data to be converted in the original data string Bit Ln: Data bit after n bits of 2-bit data to be converted in the original data string