JPS634268B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a binary data encoding method for converting an original binary data sequence into a binary code sequence suitable for recording when recording binary data on a recording medium such as a magnetic tape or a magnetic disk. Conventionally, various encoding methods have been proposed and put into practical use in order to improve the recording density when recording binary data on a recording medium such as a magnetic tape or a magnetic disk. FIG. 1 is an explanatory diagram of an example of a conventional encoding method. FIG. 1, and To indicates the bit interval. Figures b and d in the same figure are examples of conventional encoding methods;
is called the FM method (frequency modulation method), and is shown in Figure d.
is called the MFM method (Modified Frequency Modulation method). The conversion algorithm for each method is "11" in the FM method, corresponding to the original data "1" and "0".
Convert to "10". In the MFM method, "01" x "x0"
Convert to However, "×" is the complement logic (1→
0, 0 → 1). In addition, in the code series converted by each encoding method, a recording current is created so that a signal that causes magnetization reversal occurs at a "1" bit and does not cause magnetization reversal at a "0" bit, and the recording current is recorded on the medium. FIGS. 1c and 1e show recording current waveforms (NRZI signals) of code sequences encoded by the FM method (FIG. 1b) and the MFM method (FIG. 1d). In general, when recording on a magnetic medium, (a) When the magnetization reversal interval (recording wavelength) becomes short, magnetic transitions due to previous and subsequent magnetization reversals interfere with each other, causing errors when decoding reproduced signals. (b) Demodulation phase margin (TW) during reproduction with respect to recording wavelength
(described later) is also small, the same error as described above is likely to occur. Also, (c) if the recording wavelength is larger than the period of the demodulation clock signal created from the reproduced signal,
The above clock cannot be accurately generated from the reproduced signal, and the above error is likely to occur. For this reason, in general encoding systems, three of the above (a), (b), and (c) are
The following variables are given as parameters indicating abilities including items. Now, in a certain encoding method, an m-bit binary data sequence is converted into an n (n≧m)-bit binary code sequence, and then a code ``1'' arbitrarily selected from the converted code sequence is used. When the minimum value of the number of code "0" between the codes "1" that appears is d and the maximum value is k, the shortest magnetization reversal interval = m/n (d + 1) To ... (1) Longest magnetization reversal interval = m/n(k+1)To...(2) Demodulation clock period = m/nTo...(3) Demodulation phase margin (TW) = m/nTo...(4) However, To: is given by the original data period. Therefore, from the above explanation, it is desirable that the value of equation (1) is larger (from the explanation (a) above), and it is also desirable that the value of equation (4) is larger (same as above).
(From paragraph (b)). Furthermore, the smaller the ratio (equation (5)) between the demodulation clock period (equation (3)) and the longest magnetization reversal interval (equation (2)), the easier it is to create a clock from the reproduced signal. {m/n(k+1)To/m/nTo}=(k+1)……(5
) The above parameters are calculated as follows for the FM, MFM encoding method and the encoding method according to the present invention
Shown in the table.

[Table] As shown in Table 1, the encoding method according to the present invention has both the minimum magnetization reversal interval and the demodulation phase margin.
It is superior to FM and MFM systems, and also has the property of making it easy to create a demodulation clock from the reproduced signal. This invention will be explained in detail below. Table 2 shows a specific example of the conversion algorithm of the encoding method according to the present invention.

[Table] However, ×: Complement logical value of the code logical value immediately before the conversion code string (0×→01 1×→10). The conversion algorithm first separates the original data into four bits. When the separated 4-bit data pattern is included in the 13 types of original data patterns shown in Table 2 ( _S1 conversion table), this 4-bit data is converted into a 6-bit code according to the algorithm in the _S1 conversion table. Convert. However, 4-bit data
If it is not included in the _S1 conversion table, it is divided into 6 bits by adding the following 2-bit data, and this 6-bit data is converted into a 9-bit code according to the algorithm shown in the _S2 conversion table in Table 2. Convert. Here, the sign x in the converted code is the complement logical value of the code logical value immediately before the converted code string.

[Table] Observing the exchange code string converted by the above conversion algorithm, the parameter m/n = 4/6
(or6/9) and satisfies d=1 and k=7. FIG. 2 is a block diagram of a specific example of an encoding circuit that implements the encoding method according to the present invention, and FIG. 3 is a timing chart thereof. In Figure 2, the original data is connected to the atomic data clock CKI at input terminal 2.
(FIG. 3a) is input to the input terminal 1. The input data is a shift register (serial IN parallel
OUT)3, each delayed by 1 bit,
Output to data outputs Q _A to Q _H. The Q _F signal at this time is shown in Figure 3b. In addition, _the common clock CK _{2 (} third
c) is input to the input terminal 10, and the converted code clock _CK3 (FIG. 3g) is input to the input terminal 9. First, the input data is transformed into S ₁ (or S ₂
Regarding the conversion process, each output _QE to _QH of the shift register 3 enters the pattern check circuit 4, and the first 4 bits of the data to be converted correspond to one of the 4-bit patterns in the _S1 conversion table. If it does not correspond to any of the 4-bit patterns in the _S1 conversion table and is synchronized with _CK2 , a check signal d is output (Fig. 3d). . On the other hand, CK ₂ enters the S ₁ /S ₂ conversion determination circuit 6. This S ₁ /S ₂ conversion judgment circuit has a frequency dividing circuit and divides CK ₂ by 1/2 to create a 1/4 frequency divided signal of CK ₁ . By the check signal d from the pattern check circuit 4,
It has been cleared. As a result, the output of the frequency divider circuit (Fig. 3e) becomes a signal with a period of CK _1/4 when an S ₁ conversion is performed, and a signal with a period of CK _1/6 when an S ₂ conversion is performed. Therefore, the falling signal f of the output e of the frequency dividing circuit is output as the S ₁ /S ₂ conversion determination signal. Next, 5 is ROM (Read
For example, TI's SN74S471N converts the pattern output uniquely determined by the input signals _A0 to _A5 into _D0 to _D6 . The conversion algorithm of ROM5 is configured as shown in Table 3.

[Table] However, Y: Takes both logic of 1 and 0. Z: Either logic of 1 or 0 may be used. The converted pattern output is input to a shift register (parallel IN, serial OUT) 8.
Further, the _D6 output is latched by the latch flip-flop 7 for the period of the _S1 / _S2 conversion judgment signal.
Enter the serial IN input of shift register 8. In the shift register 8, the S ₁ /S ₂ conversion determination signal f is input to the SF/L (shift load) control input terminal,
The input data at that time is the original data clock _CK1 .
It is output by the 1.5x clock _CK2 (Figure 3h). As a result of this operation, the pattern (1000) of the original input data b shown in FIG. ) is understood to be converted into At this time, the ROM conversion contents are shown in Table 2.
All × values of S ₁ and S ₂ conversion are converted to “1” logic. Therefore, the signal h may have two consecutive "1's". For this process, the signal h is "11"
The signal enters the "11" pattern conversion circuit 11 which converts the pattern into the "10" pattern, becomes a normal encoded code shown in FIG. 3i, and is output to the output terminal 12. Next, a block diagram of a specific example for realizing decoding of a signal encoded by the present invention is shown in FIG. 4, and an explanatory timing chart thereof is shown in FIG.
First, the converted code string and clock j shown in FIG. 5j enter input terminals 21 and 20. Next, the shift register (serial
IN parallel OUT) 22, the signal is delayed one bit at a time, and is output from the parallel OUT terminal of the shift register 22 (the output terminal with a large amount of delay is _Q0 , hereinafter referred to as _Q1 to _Q10 (small amount of delay)). . now,
Assume that the signal k shown in FIG. 5 k is output as the signal at the _Q2 terminal. On the other hand, the signal from Q ₂ to Q ₁₀ terminals (9
line) is converted into 6-line output signals D ₀ to D ₅ by the ROM 24 (TI SN74S472N, etc.) using an algorithm that is the inverse conversion of the conversion pattern shown in Table 2.
Shift register 25 (parallel IN serial
OUT). On the other hand, the input clock j is
The 1/3 frequency divider 29 inputs a 1/3 frequency divided signal m( (shown in Figure 5 m),
This signal m becomes a timing signal for decoding. Next, the signal m is frequency-divided by the 1/2 frequency divider circuit 30 (output waveform o in FIG. 5). Next, during the synchronization period of the 1/3 frequency divider 29, the above-mentioned
When consecutive 3 bits Q ₀ to Q 2 _of the conversion code signals Q ₂ to _{Q 10} in the ROM 24 are “000” pattern.
An output signal is generated from the S ₁ /S ₂ conversion detection circuit 23,
This signal sets the output polarity of the frequency dividing circuit 30. Due to this operation, the output signal of the frequency dividing circuit 30 becomes a signal that detects S ₁ /S ₂ conversion, and
The gate output p (shown in FIG. 5p) causes the shift register 25 to latch the loaded input. By using a clock 2/3 times as large as the input clock j as the read code, decoded data r (shown in FIG. 5 r) is obtained at the serial OUT terminal 31 of the shift register 25. Although it is possible to use a clock synchronized with the input clock j using a PLL or the like as the read clock, here, it is obtained by dating the input clock g with the output of the 1/3 frequency divider 29. (Figure 5 q
) To explain this situation using the time chart in Figure 5, input code k (101001)
It will be understood that the (000010000) pattern is decoded into (1000) (001011) using decoded data j. As mentioned above, as shown in Table 1, the encoding method of the present invention has superior ability as a high-density magnetic recording method compared to other conventional modulation methods, and the hardware configuration is also very simple. Therefore, its practical value is extremely large. Note that the encoding algorithm (S ₁ and S ₂ conversion tables) used to explain the present invention is a specific example of the present invention, and the present invention can be implemented using other encoding algorithms. That is,
First, in the encoding method, any of the 16 types of patterns constituting 4-bit patterns can be selected as the specific 13 types of 4-bit data patterns to be converted into 6-bit codes. It is also clear that the correspondence of the selected patterns to the 6-bit codes may be any combination. Next, there are 12 types of 6-bit patterns obtained by adding consecutive 2-bit data to the remaining three types of 4-bit data patterns that were not selected. This 12
The 6-bit data pattern of each type is converted into a 9-bit code string, and this 9-bit code string is converted into a code ``1'' arbitrarily selected from the code string after converting the original data, and then The number of codes "0" existing between the appearing code "1" is 1 or more,
7 or less and that it is a 9-bit data pattern at the time of decoding.
There are 13 types that satisfy the two conditions of setting the sign of the 8th bit to "0". The 12 types of 6-bit data can be any combination of 12 types selected from these 13 types of 9-bit data. This invention separates a binary data string every 4 bits, and the pattern of the separated 4-bit data is
When the data corresponds to any of the 13 predetermined patterns among the 16 types of patterns consisting of 4 bits, each of the 13 types of patterns is converted to a predetermined 6-bit code, and the pattern of the 4-bit data is converted into a predetermined 6-bit code. However, when the above 13 types of patterns are not applicable, the data is separated into 6-bit data including the 2-bit data following the 4-bit data, and each of the 6-bit data is converted to a predetermined 9-bit code. , between any code "1" in the converted code string and the next code "1", one or more and seven or less codes "0"
It is possible to construct a code string in which there are , and it is possible to reduce the error occurrence rate during decoding.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the conventional FM and MFM encoding methods, Fig. 2 is a block diagram of an embodiment to which the coding method according to the present invention is applied, Fig. 3 is its timing diagram, and Fig. 4 5 is a block diagram of an embodiment for decoding a coded signal according to the present invention, and FIG. 5 is a timing diagram thereof. In the figure, 1, 9, 10, 20 are clock input terminals, 2, 21 are data input terminals, 3, 8, 2
2 and 25 are shift registers, 4 is a pattern check circuit, 5 and 24 are ROM, 6 is an S ₁ /S ₂ conversion judgment circuit, 7 is a flip-flop, 11 is an "11" pattern conversion circuit, and 12 and 31 are data output terminals. ,2
3 is an S ₁ /S ₂ conversion detection circuit, 26 is a synchronization signal input terminal, 29 is a 1/3 frequency divider circuit, 30 is a 1/2 frequency divider circuit, 3
2 is a clock output terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A binary data string is separated into every 4 bits, and the pattern of the separated 4-bit data is one of 13 predetermined patterns out of 16 patterns composed of 4 bits.
If it falls under any of the 13 types of patterns,
Each type of pattern is converted into a 6-bit code shown in the following _S1 table, and if the 4-bit data pattern does not correspond to any of the 13 types above, the 6-bit code including the 2-bit data following the 4-bit data is converted. The 6-bit data is separated into 12 predetermined 9-bit codes among the 9-bit codes shown in Table _S2 below, and any code "1" in the converted code string is converted. ”
and the next appearing code "1", forming a code string in which there are one or more and seven or less codes "0". [Table] However, in the S ₁ and S ₂ tables, "×" is the complement logic of the code logic immediately before the code string after conversion, that is, "...0×...
When it is “…”, it is “…01…”, and when it is “…1×…”, it is “…10…”.