JPS60109358A - Coding device of binary data - Google Patents

Abstract

PURPOSE:To reduce the low frequency components of a record signal by adding a connection bit to the connection part of a block after coding based on an m/n conversion code system and then controlling properly the connection bit to 1 and 0. CONSTITUTION:A binary data train is divided every (m) bits, and this divided m-bit data is converted into the code data of (n) bits whose zero run length does not exceed (k) units. Then a connection bit MB is added to the n-bit code data, and 1 and 0 of the bit MB are controlled in response to the DSV (digital summation value). Thus it is possible to obtain the code data having a small maximum magnetization inverting interval and a small low frequency component from a binary data train.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a binary data encoding device, and particularly to a coding device suitable for recording binary data on a recording medium such as a magnetic tape or a magnetic disk. It relates to a device that transforms into data.

[Prior Art] FIG. 1 is a time chart showing a conventional method for recording and reproducing binary data. In particular, FIG. 1 (a '') shows an example of the bit pattern of the original binary data, where 0°1 represents the logical bits rOJ and r1J, respectively, and To represents the bit interval. ) is N RZ (n0nl'eturn to zero) corresponding to FIG. 1(a).
) method, and as shown in the figure, the top of the rectangular wave indicates the "positive direction of magnetic flux" in the recording medium, and the bottom of the rectangular wave indicates the "negative direction of magnetic flux" in the recording medium (the same applies hereinafter).

When a record like the one shown in Figure 1(b) is read, a pulse is generated at the point of change in the magnetic flux, a signal like the one shown in Figure 1(C) is obtained, and from this the signal in Figure 1(b) is reproduced. At the same time, the bit interval To can be reproduced and
) can be demodulated into the original binary data shown in FIG.

Figure 1 ((1) corresponds to Figure 1(a)
(nonreturn to zero 1nver
ted) method. In this NRZ I method, the magnetic flux changes in response to the logical "1" bit in Figure 1 (a), and in the example shown in Figure 1, it changes from positive magnetic flux to negative magnetic flux or from negative magnetic flux. Reversing the magnetic flux in the positive direction) Theory ll! The magnetic flux does not change corresponding to the rOJ bit. When the record in Figure 1(d) is read, the pulse signal in Figure 1(e) is obtained, and from this the pulse signal in Figure 1(a) is obtained.
”) can be demodulated to the original binary data shown in FIG.

Now, consider the number of logical "O"s (referred to as zero run length) between a logical "1" and the following logical "1" in the encoded string, and let the minimum number be d, and the maximum thing 1
shall be. When using the above-mentioned NRZ 1 method, the minimum magnetization reversal interval is the logic of two consecutive bits.
1”, that is, when d=Q, the bit interval T
o, or the maximum permissible phase error when detecting the bits of the information signal, i.e. the detection window width Tw, is also the bit interval To
The reciprocal of the minimum magnetization reversal interval (d+1)TO that is equal to is called the bit rate, and an increase in the bit rate means an increase in the transmission bandwidth, which deteriorates the S/N ratio of the reproduced signal. 4 Also, the large detection window width Tw means that the reproduced signal (for example, the pulse shown in M1 diagram (e))
A clock pulse (that is, a pulse with a bit interval To) is created from , and this clock pulse is used to demodulate the reproduced signal (that is, the waveforms shown in FIG. 1(e) to FIG. 1(d) are created, Determining the original binary information signal shown in (a)) means that the tolerance for the phase error between the clock pulse and the reproduced signal can be increased, in other words the decoding ability is increased. means.

Since the NRZ I method does not add redundant bits, the TV becomes larger than other methods, but if the logic rOJ signal continues in the original signal (Fig. During this period, no pulse signal is output to the reproduced signal shown in FIG. 1(e), making it difficult to generate clock pulses from this signal.

Therefore, in order to avoid logic "0" bits from continuing for a long time in the original signal shown in Figure 1 <a>, the data string is divided into blocks of a certain number of bits, and the value of is limited. Signals are converted and recorded according to a predetermined algorithm.

As an example, the 8/9 conversion method will be explained. The original data string is separated into 8-bit units, the separated data string is defined as (×1+2+...×71×8), and this 8-bit data string is converted into data in 9 bins 1 and up. The data string after conversion is (Z + * Z2 +...Z8.z
9). FIG. 3 shows the data formats of the data string before conversion and the data string after conversion. Data column (X
I + ×2 +...×7. ×8) into the first sub-data (x2r a*X4), the second × sub-data (Xs, Xs), and the third sub-data (×+
+ ×? + ×8 >. Next, let the OR output of the first sub-data be M, that is, Ml−×2
+ x 6 +
7. According to the logic of M2, three pieces of 8-bit converted data (temporarily referred to as seventh, eighth, and ninth sub-data) are created using the encoding algorithm shown in FIG. In this way,
There is at least one logic “1” bit in each of the three conversion sub-data, and the second
As is clear from the figure, No. 7. 8th. When each of the ninth sub-data is periodically arranged in a circular manner, the maximum number of consecutive logical "0" bits is 3 or less (K = 3 >). Under the conditions shown in Fig. 2, MI XM2 = 1 is the first
The logic “1” is also present in the sub data (×2.8.
” bit is included, and MI
-1 means that the first sub-data includes a logic "1" bit, but all the bits of the second sub-data are logic rOJ, and M.

XM2-1 has logic "0" to each pin 1 of the first sub-data, but logic "1" in the second sub-data.
” bit is included, Ml XM2
=1 means that both the first sub-data and the second sub-data are logical.
This means that it does not include a bit of 1. therefore,
According to the above conditions, the encoding algorithm shown in FIG. If you create the 8th and 9th sub data, MI
When XM2 = '1, z2 is logical rIJ, z+ or Zs
At least one of orz6 is logical rIJ,z, orz6
At least one of them is h-buried rIJ1MI
When = 1, Z+ + Zs is logical r1J, Z7h+z6
or 79, at least one is logical rlJ, MIXM2
= 1, Z+ + Z4 is logic rIJ, at least one of Z7 or z8 is logic rIJ, when MIXM2-1, 11, z2, Zs, and Zs are logic "1", and the seventh
, the eighth, and the ninth sub-data are periodically arranged in a circular manner, the maximum number of consecutive logical "0" bits is 3 or less.

When the encoding algorithm shown in Fig. 2 is expressed as a logical formula, M, -X 2+X, +X, ... (2-1)
Mz=Xs+X6...(2-2) Z + -X I XMI XM2 +Ml +M2・
...(3-1) Z z -Ml XM2 +M+ XM2... (3
−2) z Il −× 8 ... (3-3) Z 4 =X
2 XMI Xtv12 +X + XM, xv.

10X, XMI xMz IVI XM2=M+Xt
vlz +×2 XM2 +X + xT7+10x,
xx2...(3-/I)Z5=X3
xM+ XM2 +lVl+ XM2+ M , X M
2 =Mz +X 3XMI -(35nZ G =X
4 XMI XM2 +X y XMI XM2+X,
× Fan + XM2 +X 7 xM+ X side.

==x, xM, XM2 →−× 7 ×M20X,
XM, XM2 ... (3-6>77-xs XM +
X FA 2 +X 2 X IVI I X M2
+x 5 XM, XM2 =X 5 XMz+X 2
X! Vl, XM2... (3-7nz6=x
, XM2 +X , xM+ XM2... (3-8) Z 9 =X 7 XMI XIVI2 +X 4 X
fvl+ XM2-X 7 xM2 +X 4 xM,
XM2+M+xM2... (3-9)
becomes.

For decoding, first bit 12 + ZS * Z
7.M when converted from FIG. 2 by the logic of 18.

You can understand the logic of M2. That is, Z2x(z
, +za)=1, then MI xM2 =1. Z2xz
If S=1, MI xM2 =1. Z 2 XZ s-
If 1, then M + xM 2 ” = '1 * Z 2
If X i7 X Z B = 1, MIXM2 = 1, and the decoded data is
50z 6z 2 z 5 +z , z 2 z ,
z 8... (4-1) x,,=z,zz (Z7 +Za,)+Z7Z2Zx
... (4-2) x 3 =zszz (Z'? +Za, >4-ZaZ
2Zs... (4-3) X, t-z 6z 2 (z, +z 8 ) +z
9z 2z.

... (4-4) X, = Z, Z2 (Z, +2'5) + Z, Z 2 Z,
.

... (4-5> X6 -z 8 z 2 (Z7 + - z 8 ) + z
6z 2z.

... (/l0) X 7 = Z g Z 2 (Z 7 + Z 6
) −4−Z 6 Z 2 Z 5+z 9z 2z
j+z, z2z, z6...<4-7) x6=z,...<4-8).

FIG. 4A is a block diagram showing a conventional encoding device that encodes a binary data string using the 8/9 conversion method. Fourth
FIG. B is a block diagram showing a conventional decoding device for decoding data encoded by the device of FIG. 4A into original data. In the figure, input terminal 1 receives original data to be encoded. Further, the clock of the original data is input to the input terminal 2. The subclock generator 4 receives the tarock from the input terminal 2 and generates a subclock for every 8 bits. The original data inputted from the input terminal 1 is inputted from the serial input terminal of the serial input parallel output shift register 5 together with the subclock generated by the subclock generator, and the first data is input from the parallel output terminal every 8 bits. Second. The third sub-data are separated and output.

Each subdata is a program array logic (hereinafter referred to as P
△ [referred to as ) 6 and the above-mentioned formula (2-1>).

According to the logic of (2-2> and equations (3-1) to (3-9), the seventh, eighth, and ninth sub-data are created.

The converted sub-data is the 7th. Parallel input serial output shift register 7 arranged in the order of the 8th and 9th sub-data
is input from the parallel input terminal of The subclock obtained from the subclock generator 4 is used as the load timing signal for this input. A modulation clock (clock with a frequency of 9/8 of the original clock) is applied to the human input signal input to the shift register 7 from the input terminal 3.
By shifting the data, encoded data (hereinafter referred to as encoded data) can be obtained from the serial output terminal 8, and this encoded data can be used for recording.

Next, the above recording is reproduced to obtain encoded data and a modulated clock. The input terminal 9 shown in FIG. 148 is given a code 1 data. Further, a modulation clock is applied to the input terminal 10. The leave clock generator 12 receives the modulated clock from the input terminal 1o and generates a subclock every 9 bits. This sub-clocker is applied to a serial input parallel output shift register 13. The encoded data input to the input terminal 9 is input from the serial input terminals of shift 1 to register 13, and every 9 bits is input from the parallel output terminal to the 7th... 8th. The ninth subdata is separated and output. Each subdata (YI" is input to AL14, and according to the logic of equations (4, -1) to C4-8 described above (x,
+ X 2 +...×7. x8) bits are created, arranged in the above order IY, and inputted from the parallel input terminals of the parallel input serial output shift register 15. The knob clock obtained from the subclock generator 12 is used as the load timing signal for this input. If the signal input to the shift register 15 in this way is input from the input terminal 11 and shifted using the original clock (8/9 frequency of the modulation clock, lock), 1q of original data can be obtained from the serial output terminal 16. I can do it.

An example of a conventional binary data encoding device has been described above using the 8/9 conversion conversion ratio method. Incidentally, in a recording/reproducing system using a rotary transformer, it is necessary that the recording signal has a small amount of low frequency components. If the low frequency component increases, the recording signal waveform will become as shown in Figure 5, and the effective recording current (the current with the magnitude indicated by the arrow in Figure 5) will vary greatly depending on the direction of current reversal.
This is far from an optimal record. The above-mentioned 8/9 conversion conversion ratio method has a large low frequency component, so it is not suitable for the above-mentioned recording/reproducing system.

Conventionally, there is an 8-10 block code conversion system as one encoding system that reduces the above-mentioned drawbacks. This conversion method uses 1 input signal for 256 types (28) of 8-bit input signals.
0pi]-conversion code. There are 252 combinations of codes in which 5 bits of the 10-bit signal are logic "1" and the remaining 5 bits are logic "0".

Cs), this code is used as a conversion code. In addition, the shortage of 4
For the street, two codes with six logic "1"s and two codes with four logic "1"s are assigned as codes.

By performing NRZ recording of the data encoded in this manner, it is possible to record almost no direct current component. However, in this encoding method, there may be a maximum of ten consecutive logic "1"s or logic rOJs, which increases the maximum magnetization reversal interval and deteriorates the decoding ability.

As is clear from the above explanation, the conventional binary arter encoding systems each have a -long length, and there is no one in which the maximum magnetization reversal interval is small and the low frequency component of the recording signal is small.

[Summary of the Invention] This invention 1 was made in order to eliminate the drawbacks of the conventional binary data encoding method, and it divides a binary data string into m bits and m-pit data is divided into m bits. is converted into n-bit code data whose zero-run length does not exceed 1 bit, and roughly equates the connection bit slot 1 to 1 bit 1 to this n-bit code data, and then equates the connection bit slot 1 to this connection bit 1. It is an object of the present invention to provide an encoding device that can convert a binary data string into code data with a small maximum magnetization reversal interval and a small low frequency component by appropriately determining logic.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

[Embodiments of the Invention] The embodiments of the present invention described below are based on the conventional 8/9 conversion conversion ratio method described above, and are based on the 9-bit 1-9 encoding attack as shown in FIG. 1 at the connection part of the block consisting of
Bits for connecting bits (hereinafter referred to as merge bits 1~)
Add MB and set the logic of this merge pit to "0" appropriately.
Alternatively, it is controlled to "1" and is a contingency that reduces the low frequency component of the recording signal.

The logic of the merge pit MB (above) is determined according to the following steps.

(1) DSV (digital sum) of the preceding encoded data (data encoded at 51')
ationValue). Furthermore, this DS
V is encoded data, for example, NRZ signal or NRZ I
(Changed to a recording current waveform like ffi?? Then this recording type) Pitch 1 of the high level part of the Y1 waveform
- is an ax between the number and the number of bits in the part I,
(IE) represents the magnitude of the frequency signal component of the recording current waveform.

That is, if DSV is O, the low frequency component of the recording current waveform is IO, and its absolute value is large. , the encoded data string is set to '1' and I ([IN; to compensate for the blurred NRZ I signal; when the high 1. Calculate the difference as DSv.

(2) The two hits from the end of the preceding encoded data are 3! l! When r00J and the leading bits 1 to 1 of the subsequent encoded data (currently encoded data) are logic 10, the merge bits I-M B 7 are set to logic 1-11.

This is to limit the maximum value K of the zero run length to 3 or less.

(3) For cases other than the case ' shown in (2) above, set the merge bit MB to logic "0" and measure the DSV of the following 9 bits of encoded data so that the polarity is the same as the DSV determined in (1) above. Only in the same case, change the merge bit MB to logic "1".

If the logic of merge bit MB is determined as above, D
Sv can be brought close to O, and the low frequency component of the recording current can be reduced.

FIG. M7 is a schematic block diagram showing an encoding device U according to an embodiment of the present invention. In the figure, this embodiment has the same configuration as the conventional encoding device shown in FIG. 4A except for the following points, and corresponding parts are given the same reference numerals and their explanation will be omitted. The original input from input terminal 1? The hexadecimal data is encoded by the 8/9 conversion conversion ratio method as in the past, and is outputted from the PAL 6 in units of 9 pits. This 9-bit encoded data is applied to the parallel input terminals of the shift j register 7. The shift register 7 inputs 9-bit encoded data using the sag clock from the sub-clock generator 4 as a load timing signal. In this way, the signal input to the shift register 7 is shifted using the modulation clock from the input terminal 3. The modulated clock applied to the input terminal 3 at this time is a clock having a frequency of 10/8 of the original clock. Therefore, the serial output terminal of the shift register 7 outputs 10 bits of serial data starting with the merge bit MB. At this time, the logic of the merge bit MB is f' OJ.

The 10-bit serial data from the shift register 7 is applied to the serial input terminal of the pattern detection section 18 and also to the first input terminal of the OR gate 21. Parallel data of 9 bins 1- from the PAL 6 is applied to the parallel input terminal of the pattern detection section 18. The pattern detection unit 18 detects that the last two bits I~ of the encoded data (preceding encoded data) from the register 7 to shift 1 are logical "OO
”, it is detected when the bit corresponding to the first bit of the encoded data from PAL 6 (following encoded data) is logic “0”, and when this pattern is detected, OR gate 2
A high level signal is output to the second input terminal of No. 1. At this time, the next 10 pins output from the shift register 7
- the first bit of the serial data (i.e. the merge bit M
The logic of e) is set to "1". This restricts the zero run length from exceeding 4. OR
The output of the gate 21 is applied to the output terminal f8 and also to the preceding DSv calculation section '17. This advance DS
The V calculation unit 11 calculates I)SV of the preceding encoded data, that is, the encoded data already output from the OR gate 2-1.
(In this embodiment, when encoded data is converted to an NRZI signal, the pitch I included in the high level part of the signal is
・Calculate the difference between the number and the number of hits included in the low level part: 'A f@. To that end, we will prepare the advance DSV performance Korean part 17.
Although not shown, it includes, for example, an up/down counter that performs a counting operation for each 1-bit output of the OR gate 21. This up/down counter is OR gate 2
When the output logic of 1 becomes 11, the up-count state and down-count state are switched. The polarity (positive or negative) of the count result of this up/down counter is given to one input of the polarity comparison circuit 20.

Also, a signal indicating whether the up/down counter is in an up-counting state or a down-counting state is transmitted to the trailing DS.
It is given to the V calculation section 19. This trailing DSV calculation unit 19
is given 9-bit parallel data from the aforementioned PAL6. The trailing DSV calculation section 19 adds the signal given from the preceding DSV calculation section 17 to the beginning of the first bit 1~ of the 9-bit parallel data from the PAL 6 as 1 pin to create parallel data of 10 bits 1~, The DSV of this 10-bit parallel data is performed.

As a result, the trailing DSVFi calculator 19 calculates DSv assuming that the merge bit MB of logic "0" is added to the 9-bit encoded data from the PAL 6. In order to perform such operations, the trailing DSV
Although not shown, the drawing unit 19 includes, for example, a ROM (read only memory). This ROM has 10 pins [
- Stores a DSV conversion table corresponding to all logical combinations. The polarity of the calculation result in the trailing DSV calculation section 19 is given to the other input of the polarity comparison circuit 20. The polarity comparison circuit 20 outputs a high-level signal to an OR gate 21 when the polarity given from the preceding DSV calculation section 17 and the polarity given from the succeeding DSV calculation section 19 match.
output to the third input terminal of. As a result, the logic of the merge bit MB of the data output from the shift register 7 is converted to "1". Therefore, the trailing DSV calculation unit 1
Code data having a DSV of a polarity opposite to the polarity of the DSv calculated in step 9 is output from the OR gate 21. Therefore, the DSV of the code data output this time decreases the absolute value of the DSV of the preceding code data. As a result, DSv is always maintained near O, and low frequency components of the recording current can be reduced.

FIG. 8 is a schematic block diagram showing an example of a decoding device that decodes the data encoded by the device of FIG. 7 into original data. In the figure, a subclock generator 12 receives a modulated clock from an input terminal 10 and generates a subclock every 10 bits.

Encoded data input from input terminal 9 is given to shift register 13 together with the subclock. In the shift register 13, 9 bits excluding the merge bit M81 are outputted in parallel to the PAL 14. In PAL14,
It is similar to the tPAL 14 shown in FIG. 4B, and converts 9-bit encoded data into 8-bit data. This 8-bit data is input to the shift register 15, shifted with the original clock input from the input terminal "I" (clock with a frequency of 8/10 of the modulation clock), and output from the serial output terminal 16. . Therefore, the original data can be obtained from the output terminal 16.

In the above-mentioned embodiment, the 8/9 conversion encoding method is modified by adding one merge bit, but in general, any conversion encoding method that can limit the maximum magnetization reversal interval can be applied to the present invention. It can be applied to That is, it can be expressed as follows using the formula.

If this invention is applied to block conversion of m bits to n bits and the zero run length is limited to K, then m bits]~ will be encoded into n+1 bits, and the zero run length will become K. Furthermore, the low frequency components of the encoded data can be reduced.

Furthermore, in the above embodiment, when calculating the DSv of the encoded data, the DSv when the encoded data is converted into an NRZI signal is calculated. Of course, it is also possible to use DSV.

[Effects of the Invention] As described above, according to the present invention, it is possible to shorten the maximum magnetization reversal interval and reduce the low frequency component of the recording current. It is possible to perform recording and playback.

[Brief explanation of the drawing]

FIG. 1 is a time chart showing a conventional method for recording and reproducing binary data. FIG. 2 is a diagram for explaining the data conversion algorithm of the 8/9 variable parsimonious encoding method. Third
The figure is a diagram showing the relationship between original data and encoded data in the 8/9 transform encoding method. FIG. 4A is a block diagram showing an example of a conventional encoding device using the 8/9 modified encoding method. FIG. 4B is a block diagram showing a decoding device for decoding data encoded by the encoding device of FIG. 4A into original data. FIG. 5 is a diagram showing a recording signal waveform when data encoded according to FIG. 4A is recorded. FIG. 6 is a diagram showing the relationship between the original data before being encoded and the data after being encoded by the encoding apparatus according to the embodiment of the present invention. FIG. 7 is a schematic block diagram showing one embodiment of the present invention. FIG. 8 shows an example of a decoding fi setting for decoding data encoded by the encoding device of FIG. 7 into original data.
! It is a schematic block diagram. In the figure, 4 is a subblock generator, 5 is a serial input parallel output shift register, 6 is a PAL, 7 is a parallel input serial output shift register, 11 is a leading DSV calculation unit, 18 is a pattern detection unit, and 19 is a trailing DSV In the arithmetic unit, 20 is a polarity comparison circuit, and 21 is an OR gate. Agent Masu Oiwa Yumaki 2 center of gravity, )'Figure □ 7・・1 □□−−=1

Claims (1)

[Claims] (1) A binary data string is divided into m bits, and each of these divided m bits of data is divided into 11+7 bits 1.
An encoding device for binary data that converts into code data consisting of , wherein there are more than 2 code bits of logic rOJ between the code bit of logic 11rlJ and the code bit of 8 logic "1" that appears next. data converting means for converting the m-bit binary data into n-bit code data that satisfies a condition that the n-bit code data is not consecutive; a 1-bit connection bit slot is added to one end of the n-bit code data; An apparatus for encoding binary data, comprising means for determining the logic of the connection bit slot so as to reduce low frequency components occurring in the encoded data without impairing the conditions. (2) The logic determining means determines the DSV of the 11+1 bit code data to which the connection bit slot whose logic is currently being determined is added (when the code data is converted into a recording current waveform, the high level of this recording current waveform is polarity (difference between the number of bits in the part and the number of bits in the low-level part), and
2. The binary data encoding apparatus according to claim 1, wherein the logic of the connection bit slots 1 to 1 is determined so that the polarity of the DSV of code data that has already been encoded is different. (3) The logic determining means converts the code data into NRZ
The binary data encoding device according to claim 2, characterized in that the difference between the number of bits in a high level part and the number of bits in a low level part when converted into a signal is determined as the DS■. . (4) The logic determining means converts the code data into NRZ
The code of binary data according to claim 2, characterized in that the difference between the number of bits in the high level part and the number of bits in the low level part when converted to an I signal is taken as the DSV. conversion device. (5) The data conversion means converts 8-bit binary data into 9-bit code data using an algorithm shown in the conversion table below. A binary data encoding device according to claim 1. However, X, ~x8 are the original data 71~z that should not be encoded
9 is encoded data M1=X 2 +X 6+X 4 M2=×, +x.