JP2675621B2 - Digital data recording method - Google Patents

Description

The present invention relates to a digital data recording method suitable for recording digital signalized video data, audio data, or the like.

[Prior Art] The EFM modulation method is well known as a modulation method for recording audio data converted into digital signals on a recording medium such as an optical disk. However, in the EFM modulation method, the number of redundant bits used for code conversion from data bits to channel bits is large, and the detection window width Twin that controls the margin against time fluctuation during data reproduction is 8/17 times the bit interval T. Therefore, it is suitable as a recording method for data with a low transfer rate such as audio data, but it is not suitable for recording data that requires a high transfer rate such as video data. It was usual to use different methods.

Generally, when recording video data converted into a digital signal, a method of shortening the data length by code compression of the video data or switching the compression mode according to the movement of the image is used. It is divided into a plurality of blocks, each block is divided into a matrix, and each pixel is sampled with the number of quantization bits according to the specified mode. Mode data is added to video data that changes with a width of up to 5 bits, and symbolized in units of 1 byte (8 bits). Next, the 1/10 plurality of byte data thus obtained is added with a 2-bit redundant bit in the 8/10 conversion circuit, code-converted into channel bits, and then NRZI-coded and recorded.

[Problems to be Solved by the Invention] According to the above-mentioned conventional digital data recording method using the 8/10 modulation code, for example, in an 8/10 conversion circuit, a parity bit is added to 8-bit data to obtain 9-bit data, By converting the obtained 9-bit data into 10-bit data according to a predetermined conversion table, it is possible to obtain 10-bit data having a DC-free characteristic and also satisfying the RLLC rule. However, this type of recording system stores a pair of main and sub conversion tables in a conversion ROM having 512 addresses, so that the DC component of the conversion data integrated by the DSV integration circuit approaches zero. Or, it is necessary to select the sub-conversion table appropriately, and the minimum sign inversion interval
Since Tmin was relatively small at 0.8T, there were problems such as not being suitable for high density recording.

[Means for Solving the Problems] The present invention is to solve the above problems, and adds collation data in byte units indicating data attributes to digital data of a plurality of bytes to form a data bit string,
Channel bit for data bit 1 (or 0), provided that the following data bit is 1 (or 0)
01 and data bits 00 (or 11), 10 (or 01), 01
For 0 (or 101), 011 (or 100), each bit is uniquely code-converted into channel bits 1010,0010,000100,100100, and sync data in byte units is added at the beginning of the data bit string code-converted into channel bits. It is characterized in that a sync block is formed by the addition, and the NRZI code is used as recording data.

[Operation] The present invention forms a data bit string by adding collation data in byte units indicating data attributes to a plurality of bytes of digital data, and non-sign inversion bits consecutively appearing in a channel bit are adjacent channel bits. The data bit string that has been subjected to 1,5 code conversion that suppresses the direct current component of the channel bit when NRZI coded to 0, including the connection part with The sync block is formed by adding sync data in byte units to the beginning of the NRZI
By encoding the recorded data, a channel bit having a minimum code inversion interval equal to the bit interval and a maximum code inversion interval three times the bit interval and having a DC component of zero without exception and error propagation is also obtained. Keep it below 4 bits.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of a digital data recording device to which the digital data recording system of the present invention is applied, and FIGS. 2 and 3 are diagrams of a 1, 5 encoder shown in FIG. 1, respectively. FIG. 4 is a circuit diagram showing an embodiment and a signal waveform diagram of each part of the circuit, and FIG. 4 is a diagram showing a correspondence relationship between data bits and channel bits converted in the conversion circuit shown in FIG.

In FIG. 1, a digital data recording device 1 includes a collation data adding circuit 2 for adding 2-byte collation data indicating an attribute of recording data to digitalized signal of n bytes, and this collation data adding circuit 2. Connected to a 1,5 encoder 3 that converts data bits into channel bits by 1,5 code conversion, and 2 bytes of sync data is added to the beginning of the output of the 1,5 encoder 3, and (n + 4 ) A sync data adding circuit 4 forming a byte sync block,
It comprises an NRZ / NRZI encoding circuit 5 for sequentially NRZI encoding a plurality of sync blocks, and the NRZI encoded data is recorded on a recording medium such as a magnetic tape or an optical disc.

In the embodiment, since video data or audio data is handled as digital data, the 16-bit breakdown of ID0 to ID15 given to the collation data is as follows. For ID0 and ID1, 00 represents video data, 01 represents audio data, and 10 and 11 are left to specify other data. Further, ID2 and ID3 represent the type of ID code, and are open to the user side except when 00 is not used. Further, ID4 and ID5 represent four kinds of field numbers 00 to 11 from 0 to 3, and ID6 and ID7 include four kinds of field numbers 00 to 11 from 0 to 3. Indicates the track number. And 16 from ID8 to ID15
The bits are defined to represent sync block addresses from 00000000 to 11111111.

By the way, the sync signal placed at the beginning of the sync block is (F348) _{H in} hexadecimal, that is, 111100110100.
Use 1000 data bits. This data bit is
By 1,5 code conversion, XXXX010010100100000100000100101
Converted to 0 channel bits. However, X is
It means indefinite data that changes depending on the last 2 bits of the immediately preceding data bit. This sync data is 14 out of 16 bits.
Since the channel bit corresponding to the bit is uniformly determined and the bit can be separated by the end bit without fail, mixing with subsequent collation data cannot occur at the time of reproduction, and the minimum code inversion interval Tmin (= T) and maximum code Inversion interval Tmax
Since (= 3T) is included, the frequency components are dispersed in a wide band, and even if a bit shift occurs during reproduction, it has an excellent feature that it is difficult to get a decoding error.

As shown in FIG. 2, the 1,5 encoder 3 first latches 8-bit data bits by a latch circuit 6 composed of a D flip-flop circuit, and then latches the latched data in a serial / serial conversion circuit 7 that follows. Convert to serial data with. The data bit converted into the serial data is subjected to a two-stage shift process in the shift register circuit 8 and then sent to the conversion circuit 9, where the data bit is converted according to the correspondence relationship shown in FIG.
The data bits are code-converted into channel bits.
The channel bits obtained by the code conversion are converted into serial data by the parallel / serial conversion circuit 11 that is shift / load controlled by the determination circuit 10 connected to the conversion circuit 9, and then sent to the sync data addition circuit 4. Be done.

In this embodiment, the clock signal CK1 of the parallel / serial conversion circuit 7 and the shift register circuit 8 is set to 43 MHz, and
Double the clock signal CK2 of the serial conversion circuit 11 to 86MHz
Further, the latch clock signal CK3 of the latch circuit 6 and the shift clock signal CK4 of the parallel / serial conversion circuit 7 are set to CK1 / 8.

By the way, the conversion circuit 9 is supplied with the outputs Qa, Qb, and Qc of each shift stage from the shift register circuit 8 which performs the two-stage shift processing, and inverts each data by the inverter 21, and a total of six types of non-conversion. The inversion data and the inversion data are appropriately combined to determine the conversion mode through the logical judgment by the five AND gate circuits 22 to 26. Here, five AND gate circuits 22 to 26 are provided so that the five kinds of correspondence relationships shown in FIG. 4 are established between the data bits and the channel bits.
If there are 5 types, it will be divided. That is, the AND gate circuits 22 to 26 have data bits of 11,00,
It plays the role of determining that it is 10,010,011, and among the input terminals A to F of the parallel-series conversion circuit 11 provided on the conversion output side, A to D excluding the grounded input terminals E and F , OR gate circuit 27 receiving outputs of AND gate circuits 23, 26, AND gate circuit 22, OR gate circuit 28 receiving outputs of AND gate circuits 23, 24, AND gate circuits 25, 26
An OR gate circuit 29 for receiving the output of is connected.

However, regarding the data bit 1, it is considered that the connection consistency between the channel bits is maintained by performing the code conversion to the channel bit 01 only when the subsequent data bit is 1. In the data bit column, 1 (1) and the subsequent bit are shown in parentheses to indicate that only the leading bit is converted into the channel bit with the condition that the subsequent bit 1 is set.

On the other hand, the determination circuit 10 includes an OR gate circuit 30 that calculates the output OR of the AND gate circuits 23 and 24, and an AND gate circuit 23.
The NOR gate circuit 31 that negates the output logical sum of ~ 26 is connected to the A input terminal and the B input terminal of the synchronous counter 32, respectively, and the Qb output indicating that the output of the synchronous counter 32 is 10 is output by the inverter 33. It is inverted and supplied to the load input terminal, and is supplied to the shift input terminal of the parallel-serial conversion circuit 11 via the AND gate circuit 35 which uses the signal obtained by inverting the clock signal in the inverter 34 as the gate signal. . That is, the synchronous counter 32 is loaded with the data given to the A input terminal and the B input terminal as an initial value at the time of receiving the load signal, and counts up the count value together with the clock signal given thereafter. Initial value is 10,01,00 corresponding to the bit number 1,2,3
It ’s different. That is, when the conversion circuit 9 converts the data bit 1 (1), the parallel-serial conversion circuit 11 is given a shift command until the synchronous counter 32 counts up the count value by 1, and the data bit 00 or For 10, the shift command is given until the count value is counted up by 2, and for the data bits 010 and 011, until the count value is counted up by 3, respectively.

Therefore, the parallel / serial conversion circuit 11 has one data bit.
When (1), the conversion operation is performed with 2-bit parallel data as one unit, when the data bit is 00,10, 4-bit parallel data is used as one unit, and when the data bit is 010,011, it is 6 bits. The conversion operation is performed for each unit of parallel data.

By the way, in the five types of channel bits shown in FIG. 4, the number of non-code inversion bits 0 appearing as a block, including the bit connection part, is in the range of 1 at the minimum and 5 at the maximum, and the channel bits are NRZI coded. When it turned into
The direct current component (DSV) is zero.

As shown in FIG. 1, the NRZ / NRZI encoding circuit 5 connected to the parallel / serial conversion circuit 11 is an exclusive OR gate that takes the exclusive OR of the latch output data of the latch circuit 5a and the input data. The latch output data (recording data) is fed back to the data input terminal via the circuit 5b, and as shown in FIG. 3 (O), the NRZI code is DC-free and has zero DSV for each channel bit. Becomes This N
The minimum sign inversion interval Tmin of the RZI code is the bit interval T, the maximum sign inversion interval Tmax is 3T, and the detection window width Twin is
It is 0.5T.

On the other hand, the data (NRZI channel bit) read out from the recording medium is separated for each sync block together with the sync data, and is sequentially latched by the latch circuit 42 in the NRZI / NRZ encoding circuit 41, and further the exclusive OR gate circuit 43. In, NRZ encoding is performed by taking the exclusive OR of the latch output data and the input data. The channel bits returned to the NRZ code are subjected to a 5-step shift process by the shift register circuit 45 in the subsequent 1,5 decoder 44, and then sent to the inverse conversion circuit 46, which corresponds to that shown in FIG. According to the relationship, the channel bits are inversely converted into data bits. The data bit obtained by the inverse sign conversion is converted into serial data by the parallel / serial conversion circuit 48 which is shift / load controlled by the determination circuit 47 connected to the inverse conversion circuit 46. Then, the data bit converted into the serial data is converted into 8-bit parallel data by the subsequent serial / parallel conversion circuit 49, further latched by the latch circuit 50 including a D flip-flop circuit, and then output as a data bit. To be done.

The clock signal used is 43MHz for CK1 and 86MHz for CK2.
MHz and CK3 are set to CK1 / 8.

By the way, the inverse conversion circuit 46 is supplied with the outputs Qa to Qf of the respective shift stages from the shift register 45 which performs the 5-step shift processing, inverts individual data by the inverter 51, and also outputs four types Qc to Qf. 5 kinds of AND gate circuits 52-
The conversion mode is determined through the logical judgment of 56. In this case, the five AND gate circuits 52 to 56 are classified into five cases so that the five kinds of correspondence relationships shown in FIG. 7 are established between the channel bits and the data bits.
That is, the AND gate circuits 52 to 56 have a role of discriminating that the channel bits are 0101, 10, 0100, and 0010,000100, respectively, and A to A of the parallel / serial conversion circuit 48 provided on the conversion output side. Of the input terminals up to C, except the grounded input terminal C, A and B have OR gate circuits 57 and AND gates 54,5 which receive the outputs of the AND gate circuits 52, 54 and 55.
An OR gate circuit 58 for receiving the output of 5 is connected.

On the other hand, the determination circuit 47 includes an OR gate circuit 59 that takes the output OR of the AND gate circuits 54 and 55, and an AND gate circuit 5
NOR gate circuit 60 which negates the output OR of 4,55,56,
The Qb output indicating that the output of the synchronous counter 61 is 10 is connected to the A input terminal and the B input terminal of the synchronous counter 61, respectively, and is supplied to the shift input terminal of the parallel-serial conversion circuit 48 and also to the inverter 62. It is configured to be inverted and fed back to its own load input terminal. That is, the synchronous counter 61 is loaded with the data given to the A input terminal and the B input terminal as initial values at the time of receiving the load signal,
Since the count value is counted up together with the clock signal CK1 applied thereafter, the initial value differs as 10,01,00 depending on the bit configuration of the channel bit. That is,
When inversely converting channel bit 0101, set the count value to 1
To give a shift command until it counts up, and to reverse-convert channel bit 0100 or 0010, give a shift command until it counts up a count value of 2, and further to reverse-convert channel bit 000100 to a data bit. , The shift command is continuously given until the count value is incremented by 3. However, no shift command is output for channel bit 10.

Therefore, the parallel / serial conversion circuit 48 has
When 01 (01) or 10, 1 bit parallel data is 1
The conversion operation is performed as a unit, and the channel bit is 01.
When 00,0010, the 2-bit parallel data is used as one unit, and when the channel bit is 000100, the 3-bit parallel data is used as one unit, and the inverse conversion operation is performed.

By the way, the data bit 010,11 should have been converted to the regular channel bit 000100,0100, and channel bit 0
It is assumed that the underline portion is reproduced by reversing the sign, such as 0 10 00,0100. In this case, erroneous data bits such as 10,010 are decoded from the reproduced data as data bits. However, in the present method, the bit error that occurs in the process of such encoding and decoding is up to 4 bits, and the error propagation can always be suppressed to 4 bits or less.

In the above embodiment, the correspondence relationship between the data bit and the channel bit in the code conversion and the inverse code conversion is
All bits of the data bits shown in Figs.
It is also possible to perform code conversion or reverse code conversion according to the correspondence shown in the figure. Also, as the sync data, channel bits corresponding to 1111001101001000, which are data bits obtained by inverting all the bits of the sync data shown in the above embodiment, can be used. Further, the collation data is not limited to 2 bytes and may be 1 byte or 3 bytes or more.

[Effects of the Invention] As described above, according to the present invention, collation data in units of bytes indicating data attributes is added to digital data of a plurality of bytes to form a data bit string, and data bit 1 (or 0) is formed. In contrast, the subsequent data bit is 1 (or 0)
Is converted to channel bit 01, and data bit 00 (or 11), 10 (or 01), 010 (or 101), 0
11 (or 100) each uniquely channel bit 101
The sync block is formed by adding the byte-unit sync data to the beginning of the data bit string that has been code-converted to 0,0010,000100,100100, and then converted to channel bits, and the NRZI-encoded data is used as the recording data. Therefore, the non-sign inversion bits that appear consecutively in the channel bits are suppressed within the range of 1 to 5 including the connection part with the adjacent channel bits, and the DC components of the channel bits when NRZI encoded are individually zero. It is possible to obtain a channel bit which has a minimum sign inversion interval which is the same as the data bit interval and a maximum sign inversion interval which is three times the bit interval and in which the DC component is zero without exception.
Moreover, except for the conditional data bit 1 (or 0) that the subsequent bit is 1 (or 0), it can be converted into a double-bit channel bit without any condition, and the DC-free characteristic can be obtained in any case. Moreover, since the conditional data bit is only selected in consideration of the connection consistency with the subsequent bits, no special device for monitoring the DSV is required, and the circuit or circuit that defines the five types of correspondence or Predetermined code conversion can be performed very efficiently using the conversion table. Further, in the decoding process, channel bit 01 is converted into data bit 1 (or 0) on condition that the succeeding channel bit is 01, and Channel bits of 10,0
100,0010,000100 is converted into data bits 0 (or 1), 11 (or 00), 10 (or 01), 010 (or 101), respectively, and data is converted from channel bits according to five correspondences. Can be converted back to bits,
Moreover, error propagation can be suppressed to 4 bits or less, which provides a data recording method suitable for recording not only audio data but also video data having a high transfer rate on a recording medium such as a magnetic tape or a disk. There is an excellent effect such as being possible.

Also, 2 bytes of data bit as sync data
Channel bits corresponding to 1111001101001000 (or 0000110010110111), for example XXXX010010100100000100000100
As in 1010, the corresponding channel bit can be uniformly set for 14 bits out of 16 bits excluding the indefinite data X which changes according to the last 2 bits of the immediately preceding data bit, and at the end bit of the sync data at the time of reproduction. Since the data can be separated, confusion with the subsequent verification data cannot occur at the time of reproduction, and since the minimum code inversion interval and the maximum code inversion interval are included in one sync data, the frequency components are dispersed in a wide band. Therefore, even if a bit shift occurs during reproduction, it is difficult to be associated with a decoding error, and the sync block can be accurately and easily specified.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a digital data recording device to which the digital data recording system of the present invention is applied, and FIGS. 2 and 3 are diagrams of a 1, 5 encoder shown in FIG. 1, respectively. Circuit diagram showing an embodiment and signal waveform diagram of each part of the circuit,
FIG. 5 is a diagram showing a correspondence relationship between data bits and channel bits converted by the conversion circuit shown in FIG.
FIG. 6 is a circuit configuration diagram showing an embodiment of a 1,5 decoder and a signal waveform diagram of each part of the circuit, and FIG. 7 is a channel bit and data which are inversely converted in the inverse conversion circuit shown in FIG. FIGS. 8 and 9 are diagrams showing bit correspondences, and FIGS. 8 and 9 are diagrams showing different correspondences between data bits and channel bits in code conversion and reverse code conversion, respectively. 1 ... Digital data recorder, 2 ... Collation data addition circuit, 3 ... 1, 5 encoder, 4 ... Sync data addition circuit, 5 ...
... NRZ / NRZI encoding circuit.

Claims (4)

(57) [Claims] 1. A data bit string is formed by adding byte-by-byte collation data indicating an attribute of data to a plurality of bytes of digital data, and the following data bit is 1 for data bit 1. To channel bit 01
For data bits 00,10,010,011, each is uniquely channel bit 1010,0010,000 100,10010.
A digital data recording method in which a sync block is formed by converting the code to 0 and adding sync data in byte units to the beginning of the data bit string that has been code-converted to channel bits, and performing NRZI encoding to form record data. 2. The digital data recording system according to claim 1, wherein the sync data are channel bits which correspond to 2-byte data bits 1111001101001000. 3. A data bit string is formed by adding byte-by-byte collating data indicating a data attribute to a plurality of bytes of digital data, and the following data bit is 0 for data bit 0. To channel bit 01
In addition, for data bits 11,01,101,100, channel bits 1010,0010,000100,10010 are uniquely
A digital data recording method in which a sync block is formed by converting the code to 0 and adding sync data in byte units to the beginning of the data bit string that has been code-converted to channel bits, and performing NRZI encoding to form record data. 4. The digital data recording system according to claim 3, wherein the sync data are channel bits corresponding to 2-byte data bits 0000110010110111.