JPH0294922A - 8/10 code converting system - Google Patents

Abstract

PURPOSE:To insert error correcting processing into code converting processing and to lighten the burden of the correcting capacity of the error correcting processing by executing code conversion while selecting a pair of main and sub conversion tables. CONSTITUTION:An error correcting processing circuit 12 adds a parity bit to the end of 8-bit data and makes the data into 9-bit data, and a 9/10 converting circuit 13 executes the code conversion so that the DSV(Digital Sum Value) integrated value of converted data can be converged to zero by properly using the pair of the main and sub conversion tables. Namely, in the main conversion table, the 9-bit data are converted into either a 10-bit balanced code having a zero DSV or a 10-bit unbalanced code having a positive DSV, and in the sub conversion table, the 9-bit data are converted into either a 10-bit balanced code or a 10-bit unbalanced code having a negative DSV. Thus, the error correcting processing can be inserted into the code converting processing, the 8-bit data can be converted into 10-bit data to have an error correcting function and DC free characteristics and satisfy an RLLC rule, and the burden of the correcting capacity of the error correcting processing can be lightened.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention has an 8-bit data and error correction function and 1)
The present invention relates to an 8/10 code conversion method for converting to 10-bit data that has C-free characteristics and satisfies the RLLC rule.

[Prior Art] Compact discs played by CI (compact disc) players employ EFM (8/14 code conversion) modulation suitable for tracking servo during signal playback. Conventional 8/14 encoder 1 shown in FIG.
has an 8/I4 conversion circuit 2 that converts 8-bit data that has undergone error correction by a CIRC encoder (not shown) into 14-bit data according to a conversion table. 8
The bit data is processed not only by the 8/I4 conversion circuit 2 but also by a combination bit candidate generation circuit 3 which generates combination bit candidates according to the bit conversion rules, and by a DS described below from among the combination bit candidates.
It is also supplied to a combination bit determination circuit 4 which determines the optimal combination bit according to the V evaluation, and the optimal combination bit determined by the combination bit determination circuit 4 is output to the combination bit insertion circuit 5 as the output of the 8/14 conversion circuit 2. By inserting the data between the 14-bit data, the 14-bit data are combined.

The 8/14 conversion circuit 2 selects two or more "0"s between "!" and "1" from among 214 combination patterns of "l" indicating inversion and "0" indicating non-inversion. It has a ROM (read-only memory) that stores a conversion table of 2" (256) patterns selected according to the bit conversion rule that the number of O's is within 10. , the input 8-bit data is converted into uniquely corresponding 14-bit data.
The combination bit candidate generation circuit 4, which generates candidates for combination bits to be interpolated into 14-bit data, generates candidates for combination bits such that, for example, the last of the preceding 14-bit data ends with "l" and the subsequent 14-bit data begins with "l". In order to deal with the situation,
By inserting a 3-bit combination bit between successive 14-bit data, consistency with bit conversion rules is achieved. Among the four possible combination bit patterns: 000°00+, 010, 100. , patterns that do not violate the bit conversion rules are supplied to the combination bit determination circuit 4 as combination bit candidates. The combination bit determination circuit 4 selects 28 bits and 3 consecutive 14-bit data from the combination bit candidates supplied from the combination bit candidate generation circuit 3.
DSV (Digital Sum Va
The pattern that minimizes lue) is selected as the optimal combination bit.

By the way, the DSV used here is a 14-pit data resistor.
The high level of the signal waveform is +1 point, the low level is 11 points,
! It represents the total score that is accumulated as the 4-bit data progresses, and the smaller the absolute value of DSV, the fewer the direct current components and low frequency components of the 14-bit data, and the more likely it is to be affected by scratches on the surface of the compact disc. Therefore, the combined bit that minimizes the DSV obtained at the end of successive 14-bit data is selected as the optimal combined bit.

[Problem to be Solved by the Invention] The conventional 8/I4 encoder 1 described above can cancel the DC component of the signal, but if a coupling bit that connects 14-bit data is included, it will be difficult to convert 8-bit data. redundant bits are required, which poses the problem of unnecessarily widening the signal transmission band, and also requires a margin (knock) to prevent code errors from occurring when the time axis of the reproduced signal fluctuates. Detection window width Tv representing margin)
However, there was a problem that the bit interval T was 0.477, which was relatively small.

On the other hand, DAT (Digital Audio T
aperecorder) uses an 8/10 code conversion method that eliminates the excessive redundancy found in EFM modulation methods and reduces redundancy to 2 bits.
Maximum code inversion interval T fl for 5.18T of encoder 1
It is attracting attention for its excellent features such as being able to shorten ax to 3.2T and being compatible with double Reed-Solomon codes used for error correction. However, in this type of 8/10 code conversion method, since the error correction code processing and the code conversion process exist independently of each other, the error correction circuit handles not only the recording/reproduction process but also the code errors that occur during the code conversion process. This poses a problem in that the original purpose of error correction, which is to reduce code errors in the recording and reproducing process, is diminished accordingly.

[Means for Solving the Problems] This invention solves the above problems, and is an 8/10 code conversion method for code converting 8-bit data into 10-bit data, in which 8 bits are aggregated into l blocks. For 8-bit data that is an integer multiple of , a Reed-Solomon code having a total length that is an integer multiple of 9 is generated, and the obtained parity data is distributed one bit at the end of each 8-bit data to generate 9.
A main conversion table that converts the 9-bit data into a 10-bit balanced code with a zero DSV or a 10-bit unbalanced code with a positive DSV, or a 10-bit balanced code. or a key conversion table that converts the DSV into a negative 10-bit unbalanced code, while selecting one of the key conversion tables so that the DSV integrated value updated each time converges to zero, and converting the code into 10-bit data. That is.

[Operation] This invention provides an integral multiple of 8 blocks aggregated into l blocks.
A Reed-Solomon code with a total length that is an integer multiple of 9 is generated for the bit data, and the resulting parity data is allocated one bit at the end of each 8-bit data to create 9-bit data. The main conversion table converts bit data into a 10-bit balanced code with zero DSV indicating the DC balance of each data item or a 10-bit unbalanced code with a positive DSV, or a 10-bit balanced code or a 10-bit unbalanced code with a negative DSV. Error correction processing is added to the code conversion process by selecting one of the sub-exchange tables to be converted to a balanced code so that the DS integrated value converges to zero during conversion, and converting the code to 10-bit data. interweaving,
Converts 8-bit data to 10-bit data that has an error correction function and DC-free characteristics and satisfies the RLLC rule.

[Embodiment 1] Regarding the embodiment of this invention, FIGS. 1 to 18
This will be explained with reference to the figures. Figures 1 and 2 are 8 of this invention.
8/10 encoder and decoder to which the G.710 code conversion method is applied - circuit configuration diagrams showing embodiments, FIGS. 3 to 18
Each figure shows a pair of main and sub conversion tables contained in the conversion ROM shown in FIG. 1.

The 8/10 encoder 11 (not shown in FIG. 1) includes an error correction processing circuit 12 that adds a parity bit to the end of 8-bit data to make it 9-bit data, and an error correction processing circuit 12 that outputs 9-bit data from this error correction processing circuit! Convert to 0 bit data 9/10
It consists of a conversion circuit 13. The error correction processing circuit 12 collects 32 pieces of 8-bit data D 32n, which are aggregated into l blocks.
D 32n+I.

For D 32n+31, let f (x)=x8+x'+z''+x'+1 be the primitive polynomial (36.32) without generating a Reed-Solomon code.
Ru. That is, the total length 36 and data length 32 of the Reed-Solomon code in the embodiment correspond to four times 9 and 8, respectively, and the four parity data P3. P2. PI and PO are defined by the following relational expression. However, α is the root of the primitive polynomial.

By the way, a total of 32 bits of parity data P3. satisfy the above relational expression. P2. Pl and PO are divided into 1 bit each in the error correction processing circuit 12, and 32 data D
32n=D is added to each end of 32n+31. That is, the eight bits from the most significant bit to the least significant bit of the parity data P3 are D32n to D32n.
32n+7 is added to the end of each.

Moreover, the parity data P2 is also D32n+8 to D32n+1 from the most significant bit to the least significant bit.
5 is added to the end of each. Similarly, parity data PI
and PO also, D 32n+16 ~ D 32n+2
3 and D 32n+24 to D 32ru31.

Therefore, the parity data regarding 8-bit data of 32 symbols is individually divided and dispersively combined at the end of each symbol, as shown in FIG.

The 9-bit data obtained by adding the parity bit to the 8-bit data in this way is the result of the following < 9/10 conversion F! It undergoes code conversion in the first path 13. The 9/10 conversion circuit I3 performs code conversion so that the DSV integrated value of the converted data converges to zero, using a pair of main and sub-conversion tables prepared in advance. Both conversion tables are hexadecimal representations of 9-bit data (000)o to (IF
F) I4 in the conversion ROM with a total of 512 addresses of H
In the main conversion table, 9-bit data is converted into a 10-bit balanced code with a DSV of 0 or a 10-bit balanced code with a DSv of positive 1.
Convert to 0-pit unbalanced code, and in the sub conversion table, 9
Bit data is converted into 10-bit balanced code or DSV is negative 10
Convert to bit unbalanced code.

The main conversion table shown in FIGS. 2 to 18 is (00
0) +(~(OF'B)H 252 9-bit data correspond to 10-bit data with DSV 0,
Furthermore, 210 9s from (OFC)u to (ICD)H
For bit data, 10-bit data with a DSV of +2 is associated, and 10-bit data with a DSV of +4 is associated with the remaining 50 9-bit data from (ICE) u to (IFF) H. . Also, regarding the sub-conversion table, there are 252 9's from (000)o to (OFB)H.
The exact same 10-bit data used in the main conversion table is made to correspond to the bit data, and 1. : (
For the 210 9-bit data from OFC)H to (lCD)H, 10-bit data with Dsv of -2 is associated, and the remaining 50 data from (ICE)H to (IFF)H 10 with DSV of -4 for 9-bit data
This corresponds to bit data. However, (OPC)+
(The following is a main conversion table and a sub-conversion table.
The bit data have a sign-inverted relationship with each other.

There are 772 types of 10-bit data obtained by conversion, but all five types of DSVO, +2° ± 4, are expressed as two's complement numbers, excluding the least significant bit "0" that is common to all 4-bit data. The high-order 3 bits are combined with the high-order side of the 10-bit data and stored in the table. For example, DS V-2 is II+ and DSV-
4 is 110.

Here, the 9-hit data obtained from the error correction processing circuit 12 is first sent to the conversion ROM 14 via the D flip-flop circuit 5 at the first stage.

Then, after being converted to 13-bit data according to either the main or sub conversion table stored in the conversion ROMIJ, the lower 10 bits and the upper 3 bits are used for the D flip-flop circuit 16 for external output and the DSV integration. It is supplied to circuit I7. The DSV integration circuit I7 is a conversion ROM
It consists of an adder circuit 18 that updates the DSV integrated value by adding the previous DSV to the upper 3 bits output of l3, and a D flip-flop circuit 19 that latches the output of this adder circuit 18, and updates the current DSV integrated value. The output of the D flip-flop circuit 19 shown in FIG.

The most significant bit of the output of the D flip-flop circuit 19 is D
It represents the positive or negative of the SV integrated value, and therefore, when the DSV integrated value is zero or positive, the selection of the sub conversion table is executed using the low level latch output of the D flip-flop circuit 19. Further, when the DS■Sv value is negative, the main conversion table is selected by the high level output of the D flip-flop circuit 19.

Now, when the DSV integrated value latched in the D flip-flop circuit 19 is 001 (=+2), the 9-bit data is (OFF) H, that is, 0111111.
Suppose that 11 is sent.

In this case, since the most significant output hit of the D flip-flop circuit 19 is "0", code conversion is performed using the sub-conversion table, and data 1 corresponding to address (OFF) u is
111110001000 is output. Note that the upper 3 bits of the output data are 10-bit data 111000
1000 DSV2 is added to the previous I) SV integrated value→2 in the DSV integrating circuit 17, and as a result, 1) the SV integrated value is returned to O.

In this way, the 9-bit data sent one after another is sent to the DS
Code conversion is performed in the direction of converging the V integrated value to zero, but for the bit interval T of 8-bit data, 1
The bit interval of 0-pit data, that is, the minimum sign inversion interval Tnin is expressed as 8/10·T (−〇, 8T).

Further, the maximum sign inversion interval T wax, which is better as it is shorter, is 1
0 bit data is 1110000000.000000
By assuming the worst case of 1111, the period in which 13 “0”s persist, that is, 13Ts+1n(1
0.4T).

In this way, the 8/10 encoder 11 generates a Reed-Solomon code with a total length of 36 symbols for 32 symbols of 8-bit data aggregated into one block, and uses the obtained parity data for each 8-bit data. Allocate one bit to the end to create 9-bit data, and then convert these 9-bit data into a 10-bit balanced code with a zero DSV or a 10-bit unbalanced code with a positive DSV, which indicates the DC balance of each data item. A DS that is updated each time a conversion is performed, either the main conversion table or the sub-conversion table that converts a 10-bit balanced code or a negative 10-bit unbalanced code.
Since the configuration is such that the V integrated value is selected to converge to zero and the code is converted to 10-bit data, error correction processing is interwoven with the code conversion process, and the 8-bit data is converted into RLLC with error correction function and DC-free characteristics. It can be converted into 10-bit data that satisfies the following rules. Furthermore, since the error correction process is combined with the code conversion process, it is possible to reduce the burden on the correction capability of the error correction process that is performed separately from the code conversion process. Furthermore, in the 9/10 code conversion, the DC component of the conversion data can be suppressed within ±4, and a pair of main and sub conversion tables are stored in the conversion 110M14, which has 512 addresses, and the DSV integration By adding the circuit 17, 10-bit data that satisfies the RLLC rule can be obtained, so it is possible to implement a PLA that takes advantage of the characteristics of a small-scale ROM and to simplify the overall circuit configuration. In addition, if used in conjunction with the DPCM (Differential Pulse Code Modulation) method, 8-bit differential data that appears frequently can be
Since the SV is converted to lθ bit data of zero, the DC component of the converted data in the common range can be suppressed as much as possible.

The decoder 2I shown in FIG. 2 decodes 10-bit data into 8-bit data, and uses the 8/10 code 5 described above.
It is the opposite of 11. Here, the reproduced 10-bit data is converted into a 10/9 conversion circuit 2 with a built-in ROM.
2, it is converted into 9-bit data, and then the error correction circuit 23
Through decoding in , error correction of up to two symbols can be performed.

In the above embodiment, the total length of the Reed-Solomon code generated in the error correction processing circuit 12 is set to 4 times 8, but if an integer k including 4 is used, then (9 = 8k)
By generating the Reed-Solomon code, k pieces of parity data PO to Pk-1 can be distributively combined bit by bit to eight pieces of 8-bit data, and 9-bit data can be obtained with just the right amount.

[Effect of the invention] As explained above, this invention has the following effects! A Reed-Solomon code with a total length of an integral multiple of 9 is generated for the 8-bit data that is an integral multiple of 8 that has been aggregated into a block, and the resulting parity data is distributed 1 bit at the end of each 8-bit data. to 9-bit data, and then convert these 9-bit data into a 10-bit balanced code with zero DSV, which indicates the DC balance of each data item, or a 10-bit unbalanced code with positive DSV, or 10 A sub-conversion table that converts either a bit-balanced code or a 10-bit unbalanced code with a negative DSV is updated every time D is converted.
By converting the code to 10-bit data while selecting such that the SV integrated value converges to zero, error correction processing is interwoven with the code conversion process, and the 8-bit data has an error correction function and DC-free characteristics, and conforms to the RLLC rule. Since error correction processing is combined with code conversion processing, it is possible to reduce the correction capacity burden of error correction processing that is performed separately from code conversion processing. /10 code conversion suppresses the DC component of converted data to within ±4, and the maximum code inversion interval that occurs when 13 bits of the same type are consecutive is set to 104/10 of the bit interval.
This makes it possible to suppress the maximum recording frequency by 10 times, and also stores a pair of main and sub conversion tables in a conversion ROM with 512 addresses, and adds a DSV integration circuit to this. Since 10-bit data that satisfies the RLLC rule can be obtained, it is possible to create a PLA that takes advantage of the characteristics of a small-scale ROM and to simplify the overall circuit configuration. When used in combination, 8-bit difference data that appears frequently is converted to 10-bit data with zero DS, so it is possible to suppress the DC component of converted data in the common use range as much as possible. be effective.

[Brief explanation of drawings]

Fig. 1.2 is a circuit configuration diagram showing each embodiment of an 8/10 encoder and decoder to which the 8/10 code conversion method of the present invention is applied, and Figs. FIG. 19 is a circuit configuration diagram showing an example of a conventional 8/14 encoder. 11,... 8/10 encoder, 12. ．． ．． error correction circuit,
13. ,．． 9/10 conversion circuit, 14° conversion ROM, l
7. , , DSV integration circuit, 21° decoder, 22. ,,1
0/9 conversion circuit, 23° error correction circuit.

Claims (1)

[Claims] Converting 8-bit data to 10-bit data 8/
10 code conversion methods, 8 that are aggregated into one block
For 8-bit data that is an integer multiple of Then, the main conversion table converts the 9-bit data into a 10-bit balanced code with zero DSV indicating the DC balance of each data or a 10-bit unbalanced code with positive DSV, or a 10-bit balanced code or D
The present invention is characterized in that one of the subconversion tables for converting to a 10-bit unbalanced code with a negative SV is selected such that the DSV integrated value updated each time the conversion converges to zero, and the code is converted to 10-bit data. 8/10 code conversion method.