JPH01175323A - 8/9 code converting system - Google Patents

Abstract

PURPOSE:To at its maximum suppress the fluctuation of a directcurrent component and to generate a highly efficient code to satisfy an RLLC rule by executing a code conversion as selecting one conversion table out of a pair of conversion tables so that DSV count value updated every time of conversions may converge on 0. CONSTITUTION:8-bit data pass through a D flip flop circuit 12, separated into less significant 9 bits and more significant 5 bits in accordance with the conversion table in a converting ROM 13 and supplied to a D flip flop circuit 14 and a DSV counting circuit 15. 9-bit data after the code conversion is divided by whether a DSV(Digital Sum Variation) to show their direct current balance is positive or negative and the conversion tables made to correspond in sequence from the smaller absolute value of the DSV with a middle value between the maximum value and the value of the 8-bit data as the center are prepared. The code conversion is executed as selecting one conversion table out of the pair of conversion tables so that the DSV count value updated every time of the conversions may converge on 0. Thus. the direct-current component of a signal is canceled as keeping the DSV count value within a fixed limitation frame and the highly efficient code to satisfy the RLLC(run length limitation code) can be generated.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is an 8/8/8 suitable for digital processing of audio and video.
9 concerning the code conversion method.

[Prior Art] A compact disc played by a CD (compact disc) player employs EFM (8/14 code conversion) recording suitable for tracking servo during signal playback. Conventional 8/14 encoder l shown in FIG.
has an 8/14 conversion circuit 2 that converts 8 data bits that have undergone error correction by a CIRC encoder (not shown) into 14 channel bits according to a conversion table. The data bits are processed not only by the 8/14 conversion circuit 2 but also by the combination bit candidate generation circuit 3 which generates combination bit candidates according to the bit conversion rules, and the combination bit which determines the optimal combination bit from among the combination bit candidates according to the DSV evaluation described below. It is also supplied to the determination circuit 4, and the optimal combination determined by the combination bit determination circuit 4 is inserted between the channel bits that are the output of the 8/14 conversion circuit 2 in the combination bit insertion circuit 5. Channel bits are combined.

The 8/I4 conversion circuit 2 selects from among 214 combination patterns of “1” indicating inversion and “0” indicating non-inversion, “two or more “O”s are present between “l” and “l”. It has a ROM (read-only memory) that stores a conversion table of 2'' (256) patterns selected according to the bit conversion rule that the number of zeros is within 10. , the input data bits are converted into uniquely corresponding channel bits.Furthermore, the combination bit candidate generation circuit 4, which generates candidates for combination bits to be inserted between channel bits, converts the input data bits into uniquely corresponding channel bits. In order to cope with the case where the channel bit ends with "lo" and the following channel bit starts with "I", 3 bits are inserted between the adjacent channel bits to ensure consistency with the bit conversion rules. Among the four types of putters that can be considered as combination bits: 1000,001,010.100 (7),
Patterns that do not violate the bit conversion rules are supplied to the combination bit determination circuit 4 as combination bit candidates. The combination bit determination circuit 4 indicates the DC component of the signal for 31 bits, which is a total of 28 successive channel bits and 3 combination bits, from among the combination bit candidates supplied from the combination bit candidate generation circuit 3. DSV (Digit
The pattern that minimizes Al Sun+ Variation) is selected as the optimal combination bit.

By the way, the DSV used here represents the total number of points accumulated as the channel bits progress, with the high level of the channel bit waveform being +1 point and the low level being 11 points, and the smaller the absolute value of the DSV, the higher the score. The channel bits have fewer direct current components and low frequency components, which makes them less susceptible to scratches on the surface of the compact disc, so the combined bit that maximizes the DSV obtained at the end of successive channel bits is , is selected as the optimal combination bit.

[Problems to be Solved by the Invention] The conventional 8/I4 encoder 1 described above can cancel the DC component of the signal, but if the coupling bits that connect channel bits are included, the conversion of data bits takes a considerable amount of time. Redundant bits are required, which poses the problem of unnecessarily widening the signal transmission band.Also, there is a detection method that indicates the margin (jitter margin) to prevent code errors from occurring when the time axis of the reproduced signal fluctuates. There were problems such as the window width Tv being relatively small at 0.47T relative to the bit interval T.

Also, the redundancy is reduced by 4 bits, and the 5.
The 8/I O encoder with the maximum code inversion interval T max shortened to 3.2T compared to 18T has the minimum code inversion interval Ti1
Because it is relatively small like nh40, 8 T,
There are problems such as the maximum recording frequency becoming high, the resolution of the recording system having to be increased, and being unsuitable for high-density recording, and the minimum sign inversion interval being more important than the detection window width Tw. Therefore, the 1 and 5T encoders that realize Tm1n==1,5T also have problems such as not being DC-free.

[Means for Solving the Problems] The present invention solves the above problems, and is an 8/9 code conversion method for code converting 8-bit data to 9-bit data. The bit data is divided according to whether the DSV indicating its DC balance is positive or negative, and the values are arranged in descending order of the absolute value of the DSV, with the value midway between the maximum and minimum values of each 8-bit data as the center. A method characterized by preparing conversion tables, and performing code conversion while selecting one conversion table from the pair of prepared conversion tables so that the DSV integrated value that is updated every time the conversion converges to zero. It is.

[Operation] This invention divides the 9-bit data after code conversion depending on whether the DSV indicating the DC balance is positive or negative, and divides the 9-bit data into 9-bit data based on whether the DSV indicating the DC balance is positive or negative, and divides the 9-bit data into 9-bit data based on the value between the maximum value and the minimum value of the 8-bit data. , a conversion table is prepared in order of decreasing absolute value of DSV, and one conversion table is selected from the pair of prepared conversion tables so that the DSV integrated value updated each time the conversion converges to zero. By performing code conversion while maintaining the DSV integrated value, the DC component of the converted signal is canceled out while keeping the DSV integrated value within a certain limit, making it possible to generate a high-efficiency code that satisfies the RLLC rule.

[Example] Examples of the present invention will be described below with reference to Figure 1 (not shown) and Figure 9.
This will be explained with reference to the figures. FIG. 1 is a circuit configuration diagram showing an embodiment of an 8/9 encoder to which the 8/9 code conversion method of the present invention is applied, and FIGS. This is a conversion table used for code conversion of the /9 encoder.

In FIG. 1, the 8/9 encoder 11 converts the code of 8-bit data into 9-bit data, and its operating principle is based on the DC balance of the 9-bit data after code conversion.
A pair of conversion tables A and B are prepared depending on whether the SV is positive or negative, and the DSV is updated every time the conversion is performed.
The purpose is to select one conversion table A or B depending on whether the integrated value is positive or negative, and perform code conversion so that the DSV integrated value converges to zero. Conversion tables A and B are the intermediate value (7F) between the maximum value (FF) H and the minimum value (00) o of 8-bit data.
9-bit data centered on H, (80)H, and its DSV
They are arranged in order of decreasing absolute value. In the embodiment, as shown in FIGS. 2 to 9, 2 expressed in hexadecimal
Using 56 pieces of 8-bit data as a read address, 9-bit data in which each bit has an inverted relationship with each other is stored in tables A and B.
Regarding the number of sign inversions INV of bit data, consideration is given so that the larger the number of sign inversions INV is, the more the value can be obtained on the intermediate value side of 8-bit data.

Note that the DSV of the conversion data is expressed as a two's complement number, combined with the upper part of the 9-bit data as 5-bit data, and stored in the table.

The 8-bit data is first sent to the conversion ROM 13 that stores tables A and B via the D flip-flop circuit 12 at the first stage. After it is converted into 14-bit data according to conversion table A or B in the conversion ROM 13, it is decomposed into the lower 9 bits and the upper 5 bits, which are respectively connected to the D flip-flop circuit I4 for external output and the DSV integration for internal feedback. The signal is supplied to the circuit 15. DSV integration circuit 15
is the previous D to the upper 5 bits output of the conversion ROM13.
It consists of an adder circuit 16 that updates the DSV integrated value by adding SV, and a D flip-flop circuit 17 that compares the output of this adder circuit 16, and the output of the D flip-flop circuit 17 that represents the current DSV integrated value is added. It is used as the augend input of the circuit 16.

The most significant bit of the output of the D flip-flop circuit 17 is D
Takes “0°” or “1” depending on the positive or negative of the SV integrated value,
The data is supplied to the conversion ROM 13 via the polarity inversion circuit I8 as data for selecting a conversion table in the conversion ROM 13. In the embodiment, the output of the polarity inversion circuit 18 is “0”.
” (that is, when the DSV integrated value is negative)
is configured such that when conversion table A is selected and is "1" (that is, when the DSV integrated value is positive or zero), conversion table B is selected.

Now, if the DSV integrated value is 11011, that is -
5, the address (00
) corresponds to H. ooooooo.

Suppose that you have been sent. In this case, since the output of the polarity inversion circuit I8 is "0", conversion table A is selected and data 0011111 corresponding to address (00)H
1111110 is output.

The upper 5 bits of the output data at this time, ootz, represent DSV7 of the 9-bit data 111111110, which is added to the previous DSV integrated value -5 in the DSV integration circuit 15, and as a result, the DSV integrated value becomes 2. Change.

When the DSV integrated value becomes 2, the output of the polarity inversion circuit 18 becomes "1", so that the next 8-bit data is always code-converted by the conversion table B. Therefore, the DSV integrated value never exceeds -9 to +8, and the converted output never has a DC component.

In this way, data bits sent one after another are always D
Code conversion is performed in the direction of converging the SV integrated value to zero, but for the bit interval T of 8-bit data,
The bit interval of 9-bit data, that is, the minimum sign inversion interval T min is expressed as 8/9·T (phrase Q, 89T).

The maximum sign inversion interval T wax, which should be as short as possible, is 10000000 for 9-bit data.
Assuming the worst case of 0.000000000.000011111, the period in which 21 "0"s persist, ie, 2 lTm1n (-18,8T).

In this way, the 8/9 encoder 11 converts the 9
The bit data is divided according to whether the DSV indicating its DC balance is positive or negative, and the values are arranged in descending order of the absolute value of the DSV, with the value midway between the maximum and minimum values of each 8-bit data as the center. Conversion tables A and B are prepared, and one of the conversion tables A and B is selected from the pair of conversion tables A and H so that the DSV integrated value updated each time the conversion converges to zero. Since the configuration is configured to convert, what is the 8-bit data that appears frequently?
It is possible to convert the code to 9-bit data with a small absolute value of SV, and by performing table selection for the purpose of zero convergence, the DSV integrated value of the 9-bit data obtained by code conversion can be opened to a certain extent. It is possible to suppress fluctuations in the DC component to the maximum while limiting it within the frame -9 to +8,
As a result, the minimum code inversion interval T of the signal waveform after code conversion
RLL with a min of 0.89T, a maximum sign inversion interval Tmax of 18.8T, and a detection window width Tw of 0.89T.

C (Run Length Limted Code
) can be easily generated.

In addition, since the 8-bit data that appears frequently is code-converted into 9-bit data that has a high number of sign inversions, it is possible to suppress the length of the sign inversion interval as much as possible and prevent deterioration of recording and playback characteristics. . Furthermore, only two conversion tables are required for 8-bit data, so appropriate 9-bit data can be read with 256 addresses, which allows small-scale R
It is easy to create a PLA that takes advantage of the characteristics of OM.

In the above embodiment, the pair of conversion tables A and B stored in the conversion ROM 13 can be processed in various ways, and the way in which 9-bit data is combined with 8-bit data can also be freely changed as necessary. be able to.

[Effects of the Invention] As explained above, the present invention divides 9-bit data after code conversion depending on whether the DSV indicating the DC balance is positive or negative, and divides the 9-bit data after code conversion into the maximum value of h8-bit data. A conversion table is prepared in which the absolute value of DSV corresponds to the smallest value, centering on the intermediate value between Since code conversion is performed while selecting one of the conversion tables so that the data converges to By executing the desired table selection, it is possible to limit the DSV integrated value of 9-bit data obtained by code conversion within a certain limit, and to suppress fluctuations in the DC component to the maximum extent possible. It is possible to easily generate a high-efficiency code in which the minimum sign inversion interval and maximum sign inversion interval of the signal waveform after code conversion satisfy the RLLC rule, and there are two types of conversion tables for 8-bit data. Therefore, appropriate 9-bit data can be read out using 256 addresses, and this provides excellent effects such as easy implementation of a PLA that takes advantage of the characteristics of a small-scale ROM.

[Brief explanation of the drawing]

Figure 1 shows an 8
2 to 9 are circuit configuration diagrams showing one embodiment of the /9 encoder, and each of them is a diagram showing a conversion table used for code conversion of the 8/9 code converter shown in FIG. The diagram is
FIG. 1 is a circuit configuration diagram showing an example of a conventional 8/14 encoder. 11,... 8/9 encoder, 13. ．． ．． Conversion ROM, 15
．． ,,DSV integration circuit.

Claims (1)

[Claims] Converting 8-bit data to 9-bit data 8/9
This is a code conversion method that divides the 9-bit data after code conversion depending on whether the DSV indicating the DC balance is positive or negative, and centers the value between the maximum and minimum values of each 8-bit data. , a conversion table is prepared in order of decreasing absolute value of DSV, and one conversion table is selected from the pair of prepared conversion tables so that the DSV integrated value updated each time the conversion converges to zero. The 8/9 code conversion method is characterized in that code conversion is performed while