JPH02276315A - 8/10 code conversion system - Google Patents

Abstract

PURPOSE:To attain the making of a circuit into PLA utilizing the feature of a ROM of small scale and the simplification of the whole of the circuit by mixing an error correction processing in a code conversion processing, and converting data of eight bits to NRZI data of ten bits provided with an error correction function and DC-free characteristic and satisfies an RLLC rule. CONSTITUTION:An 8/10 encoder 11 is comprised of an error correction processing circuit 12 which sets the data of eight bits as the data of nine bits by attaching a parity bit on the end of the data of eight bits, and a 9/10 conversion circuit 13 which converts the data of nine bits that is the output of the error correction processing circuit to the data of ten bits. The data of nine bits that is the one targeted to be converted is sent to a conversion ROM 14 via a D flip-flop circuit 15. And after it is converted to the data of 14 bits according to either a main or sub conversion table stored in the conversion ROM 14, the low-order ten bits and the high-order four bits of the data are supplied to a parallel-serial conversion circuit 16 and a table selection circuit 17, respectively.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention has an error correction function and DC-free characteristics for 8-bit data, and satisfies the RLLC rule! The present invention relates to an 8/10 code conversion method for converting to θ bit data.

[Prior Art] A compact disc played by a CD (compact disc) player employs EFM (8/14 code conversion) modulation suitable for tracking servo during signal playback. The conventional 8/14 encoder 1 shown in FIG. 19 includes an 8/14 conversion circuit 2 that converts 8-bit data that has undergone error correction by a CIRC encoder (not shown) into 14-bit data according to a conversion table. have , 8
The bit data is processed not only by the 8/14 conversion circuit 2 but also by the combination bit candidate generation circuit 3 which generates combination bit candidates according to the bit conversion rules and by the DS described below from among the combination bit candidates.
It is also supplied to a combination bit determination circuit 4 which determines the optimal combination bit according to the V evaluation, and the optimal combination bit determined by the combination bit determination circuit 4 is output to the combination bit insertion circuit 5 as the output of the 8/14 conversion circuit 2. By inserting the 14-bit data between the 14-bit data, the 14-bit data are combined.

The 8/14 conversion circuit 2 selects from among 214 combination patterns of "1" indicating inversion and "O" indicating non-inversion, "two or more "O" between "1° and °l°". It has a ROM (read-only memory) that stores a conversion table of 2'' (256) patterns selected according to the bit conversion rule that the number of O's is 10 or less. In this way, the manually generated 8-bit data is uniquely converted into corresponding 14-bit data. Also,
The combination bit candidate generation circuit 4, which generates candidates for combination bits to be interpolated into 14-bit data, is configured to generate combination bit candidates when, for example, the preceding 14-bit data ends with "11" and the subsequent 14-bit data begins with "I". In order to be able to deal with
By inserting a 3-bit combination bit between successive 14-bit data, consistency with bit conversion rules is achieved. , patterns that do not violate the bit conversion rules are supplied to the combination bit determination circuit 4 as combination bit candidates. The combination bit determination circuit 4 selects 28 bits and 3 consecutive 14-bit data from the combination bit candidates supplied from the combination bit candidate generation circuit 3.
DSV (Digital Sum Va
The pattern that minimizes lue) is selected as the optimal combination bit.

By the way, the DSV used here is defined as +1 point for the high level and 11 points for the low level of the signal waveform of 14-bit data.
It represents the total score that is accumulated as the 14-bit data progresses, and the smaller the absolute value of DSV, the fewer the direct current components and low frequency components of the 14-bit data, and the more likely it is to be affected by scratches on the surface of the compact disc. Therefore, the combined bit that minimizes the DSV obtained at the end of successive 14-bit data is selected as the optimal combined bit.

[Problem to be solved by the invention [L] The conventional 8/14 encoder l described above can cancel the DC component of the signal, but if a combination bit that connects 14-bit data is included, the conversion of 8-bit data is difficult. This requires a considerable amount of redundant bits, which poses the problem of unnecessarily widening the signal transmission band, and also requires sufficient margin to prevent code errors from occurring when the time axis of the reproduced signal fluctuates. There were problems such as the detection window width T, which represents the knock margin, was relatively small at 0.47T relative to the bit interval T.

On the other hand, DAT (Digital Audio T
aperecorder) uses an 8/10 code conversion method that eliminates the excessive redundancy found in EF and M modulation methods and reduces redundancy to 2 bits.
4 Encoder 1 5. Maximum sign reversal interval T m for I8T
It is attracting attention for its excellent features such as being able to shorten ax to 3.2T and being compatible with double Reed-Solomon codes used for error correction. However, in this type of 8/10 code conversion method, error correction code processing and code conversion processing exist independently of each other, so code errors occurring not only in the recording/reproduction process but also in the code conversion process are processed by the error correction circuit. This poses a problem in that the original purpose of error correction, which is to reduce code errors in the recording and reproducing process, is diminished accordingly.

[Means for Solving the Problems] This invention solves the above problems, and is an 8/10 code conversion method for code converting 8-bit data into 10-bit data, in which 8 bits are aggregated into l blocks. For 8-bit data that is an integer multiple of
A main conversion table that converts the 9-bit data into a 10-bit balanced code with a zero DSV or a 10-bit unbalanced code with a positive DSV, or a 10-bit balanced code. or a sub-conversion table for converting to a 10-bit unbalanced code with a negative DSV, the code is converted to 10-bit data while selecting one of the sub-conversion tables so that the DSV integrated value updated each time the conversion converges to zero, and then the code is converted to 10-bit unbalanced code. The 10-bit data obtained by conversion is N
It is characterized by RZI encoding.

[Operation] This invention provides an integral multiple of 8 blocks integrated into one block.
A Reed-Solomon code with a total length that is an integer multiple of 9 is generated for the bit data, and the resulting parity data is allocated one bit to the end of each 8-bit data to create 9-bit data, and then these 9 bits are data, NRZI
D indicates the DC balance of individual data when encoded
A main conversion table that converts a 10-bit balanced code with an SV of zero or a 10-bit unbalanced code with a positive DSV, or 1
While selecting either a 0-bit balanced code or a sub-conversion table that converts DSV into a negative 10-bit unbalanced code so that the DSV integrated value updated each time the conversion converges to zero,
By converting the code to 10-bit data and finally performing NRZI encoding, error correction processing is interwoven with the code conversion process, converting the 8-bit data into 10-bit NRZI data that has an error correction function, DC-free characteristics, and satisfies the RLLC rule. Convert.

[Example] Examples of the present invention will be described below with reference to FIGS. 1 to 18.
This will be explained with reference to the figures. Figure 1.2 shows 8/8 of this invention.
! The circuit configuration diagrams illustrating each embodiment of the 8/10 encoder and decoder to which the O code conversion method is applied, FIGS. 3 to 18, are the main side in which the conversion ROM shown in FIG. FIG. 3 is a diagram showing a pair of conversion tables.

The 8/10 encoder shown in Figure 1! ■ is an error correction processing circuit that adds a parity bit to the end of 8-bit data to create 9-bit data! 2 and 9/10 to convert the output 9-bit data of this error correction processing circuit into 10-bit data.
It consists of a conversion circuit 13. The error correction processing circuit 12 collects 32 pieces of 8-bit data D 32n into an I block,
D 32n+1.

For D 32n+31, a Reed-Solomon code is generated with f (x)=x"+x'+x'+x"+1 as a primitive polynomial (36.32). That is, the total length 36 and data length 32 of the Reed-Solomon code in the embodiment correspond to four times 9 and 8, respectively, and the four parity data P3. P2. PI and PO are defined by the following relational expression. However, α is the root of the primitive polynomial.

By the way, a total of 32 bits of parity data P3. satisfy the above relational expression. P2. Pi and PO are divided into 1 bit each in the error correction processing circuit 12, and 32 data D
32n=D is added to each end of 32n+31. That is, the eight bits from the most significant bit to the least significant bit of the parity data P3 are D32n to D32n.
32n+7 is added to the end of each.

Moreover, the parity data P2 is also D32n+8 to D32r++ from the most significant bit to the least significant bit.
15 is added to the end of each. Similarly, parity data P
I! : Regarding PO, D 32n + 16 ~ D 32
It is divided and allocated to n+23 and D 32n+24 to D 32r++31, respectively.

Therefore, the parity data regarding 8-bit data of 32 symbols is individually divided and dispersively combined at the end of each symbol, as shown in FIG.

The 9-bit data thus obtained by adding the parity bit to the 8-bit data undergoes code conversion into 10-bit data in the subsequent <9/10 conversion circuit 13. In this code conversion, a pair of main and sub conversion tables is used, and code conversion is performed such that the DSV integrated value converges to zero when 10-bit data is NRZI encoded.

The main and sub conversion tables are stored in 14 conversion ROMs with 512 addresses from (000)s to (IFF)H, which are hexadecimal representations of 9-bit data. After converting the data to NR
The 10-bit data obtained by ZI encoding is converted into a balanced code with a zero DSV or an unbalanced code with a positive DSV, and in the sub-conversion table, the 9-bit data is converted into the above DSV.
The DSV is converted into a balanced code with zero, or an unbalanced code with a negative DSV. However, in the NRZ I code, bit “Oo” means sign non-inversion, and bit “1” means sign inversion, so even if the starting bit (S?”B) is high, even if it is the same 10-bit data, Alternatively, the DSV differs depending on the row. Therefore, assuming that the start bit of 10 bit data is low level, the difference in the number of high and low bits when 10 bit data is NRZI encoded is shown here as DSV. Also, since whether the end bit is high or low is an essential condition for table selection in the subsequent code conversion, an item called INV is provided.
If the end bit is non-inverted with respect to the start bit, then IN
It is defined that V is set to "0', and conversely, if it is inverted, it is expressed as INV"lo.

The main conversion table shown in FIGS. 3 to 18 is (00
For the 252 9-bit data from 0)H to (OFB)H, correspond to the 10-bit data with DSV 0, and further to the 210 9-bit data from (OFC)H to (ICD)H. corresponds to the 10-bit data with DSv +2, and the remaining 5 from (ICE)H to (IFF)u
10-bit data with a DSV of +4 is made to correspond to 0 9-bit data. In addition, for the sub-conversion table, the 252 9-bit data from (000)s to (OFB)H are matched with the exact same 10-bit data used in the main conversion table, and (OFC)H
For the 210 9-bit data from ~(ICD)H, 10-bit data with a DSV of -2 is associated, and for the remaining 50 9-bit data from (ICE)H ~ (IFF)H. This corresponds to 10-bit data with a DSV of -4. Note that (OFC)H and below are tables A and B.
The 10-bit data for the same 9-bit data is
Only the most significant bits are inverted, and the bits below are exactly the same.

In the case of the embodiment, there are 772 types of 10-bit data obtained by conversion, but there are 5 types of DSVO2±2. +4
are all expressed as two's complement numbers, and all of the 44-bit data is 0 in common, excluding the least significant bit, and only the upper 3 bits are combined with the upper side of the 10-bit data and stored in the table. be. For example, DSV-2 is 111
and DSV-4 is 110. Furthermore, INV is combined with the most significant 10-bit data to which DSV is added and stored in the table.

Here, the 9-bit data to be converted is first sent to the conversion ROM 14 via the first-stage D flip-flop circuit I5. Then, after being converted into 14-bit data according to either the main or sub conversion table stored in the conversion ROM 14, the lower 10 bits and upper 4 bits are
Parallel/serial conversion circuit 16 and table selection circuit, respectively! 7
supplied to Note that the selection of the conversion table is based on the positive/negative of the DSV integrated value obtained as a result of the code conversion performed directly, and the high or low of the start bit.
A logical operation is performed in the NOR gate circuit 18, and the operation is performed according to the result of the operation.

DSV integration is performed by three exclusive OR gate circuits 19, 20, and 21 that non-invert or invert each bit of the DSV obtained from the conversion ROM 14 depending on whether the start bit is low or high, and these circuits. ! The DSV with positive and negative signs from 9 to 21 is the previous DS
Addition circuit 2 that adds to the V integrated value to update the DSV integrated value
2 and the D flip-flop 1 circuit 23 which latches the output of the adder circuit 22 and uses the latched data as the addend input of the adder circuit 22.

The start bit, which is one input of the exclusive OR gate circuits 19 to 21, is determined when the conversion table is selected. It is obtained by taking the exclusive OR in the circuit 25, and if the start bit is "0", the exclusive OR gate circuits 19 to 21 do not perform sign inversion and the start bit is "l".
Perform sign inversion when . Note that this sign reversal is
This means adding a negative sign to the DSV expressed in two's complement, and the starting pid 1' is also supplied to the carry input terminal CI of the adder circuit 22.

By the way, the most significant bit output from the D flip-flop circuit 23 represents the positive/negative of the DSV integrated value, and as described above, the positive/negative of the DSV integrated value and the low or high of the start bit determine the conversion table selection condition. . Here, depending on the low/high level of the operation result of the exclusive NOR gate circuit 18 which negates the exclusive OR of the output most significant bit of the D flip-flop circuit 23 and the start bit,
This allows the secondary translation table to be selected. That is, when INV of 10-bit data is "1",
Since the start bit of the subsequent 10-bit data is inverted,
The start bit, which is the output of the D flip-flop circuit 24, is inverted. Then, when the start bit is 10'' (low level) and the DS integrated value is positive, the sub conversion table is selected, and if it is negative, the main conversion table is selected, and the D
SV will also be added up as it is listed in the conversion table. on the other hand,
When the start bit is °1" (high level), contrary to the above, the main conversion table is selected when the DSV integrated value is positive, and the sub conversion table is selected when it is negative, and the DSV is also converted. The values listed in the table are integrated by reversing the sign.

In this way, the 9-bit data latched by the D flip-flop circuit 15 is successively code-converted into 10-bit data in a direction that causes the DSV integrated value when NRZI-encoded to converge to zero. Then, the 10-bit data obtained by the conversion is converted from parallel data to serial data in the subsequent parallel/serial conversion circuit 16, and then converted into NRZI data.
The signal is sent to the encoding circuit 26. NRZI encoding circuit 2
6 is an exclusive OR gate circuit 2 that receives 1o bit data sent from the parallel/serial conversion circuit I6.
7 is provided in the feedback path connecting the Q output terminal and the data input terminal of the D flip-flop circuit 28, which converts the NRZ code into the NRZI code and outputs it as final recording data.

By the way, for the bit interval T of 8-bit data, 10
Bit interval of bit data, that is, minimum sign inversion interval T
Sin is expressed as 8/1OT (=0.BT).

Also, the maximum sign inversion interval T saw, which is said to be better as it is shorter, is
o,ooooootoo.

Assuming the worst case, it is possible to suppress the period during which "1" indicating sign reversal and <11 "0"s following it persist, that is, l 2Tw+1n (=9.6T).

In this way, the 8/1O encoder 11 generates a Reed-Solomon code with a total length of 36 symbols for the 32 symbols of 8-bit data aggregated into l blocks, and uses the obtained parity data for each 8-bit data. One bit is allocated to the end to create 9-bit data, and then these 9-bit data are encoded into NRZI encoded data, which is either a 10-bit balanced code with zero DSV indicating the DC balance of each data, or DS.
Either a main conversion table that converts to a 10-bit unbalanced code with a positive V or a secondary conversion table that converts a 10-bit balanced code or a 10-bit unbalanced code with a negative DSV,
Since the configuration is such that the DSV integrated value that is updated every time the conversion converges to zero, the code is converted to 10-bit data, and the last C is NRZI encoded, error correction processing is interwoven with the code conversion process. , 8-bit data with error correction function, DC-free characteristics, and 10 pins that satisfy the RLLC rule)
Can be converted to NRZ I data.

Furthermore, since the error correction process is combined with the code conversion process, it is possible to reduce the burden on the correction capacity of the error correction process that is performed separately from the code conversion process. Furthermore, 9/
In the 10 code conversion, the DC component of the conversion data can be suppressed within ±4, and a pair of main and sub conversion tables are stored in the conversion ROM 1A having 512 addresses, and the table selection circuit 17 is connected to the conversion table. By adding RLLC
Since 10-bit data satisfying the rule can be obtained, the small-scale R
It is possible to utilize the characteristics of OM in PLA and to simplify the overall circuit configuration. In addition, when used in conjunction with the DPCM (differential pulse code change m) method, 8-bit differential data that appears frequently is converted to 10-bit data with zero DSv, so the DC component of the converted data in the common range is This can be suppressed as much as possible.

The decoder 31 shown in FIG. 2 includes a 10/9 conversion circuit 3 that converts 10-bit NRZl data into 9-bit NRZ data.
2, and an error correction processing circuit 33 that performs error correction processing on the converted 9-bit data to produce 8-bit data. 8 10-bit NRZ I read from recording media, etc.
The data is transferred to the D flip flow circuit 34 and
NRZ encoding circuit 3 consisting of a sive-or gate circuit 35
6, the data is converted into 10-bit NRZ data. next,
It is converted into parallel data by the serial/parallel conversion circuit 37,
After being converted into 9-bit data in a conversion ROM 38 containing a subsequent conversion table, it is latched into a D flip-flop circuit 39 for latching and sent to an error correction processing circuit 33. The error correction processing circuit 33 collects the parity data distributed in I-bit units at the end of the 9-bit data, and generates a total of 32 bits of parity data PO~
Error correction processing is performed using P3, and errors are corrected for up to two symbols. In addition, in the magnetic recording and reproducing system,
NRZI data can be reproduced using a partial response method, and even if sign inversion occurs in the read data, accurate data can be reproduced.

In the above embodiment, the error correction processing circuit! The total length of the Reed-Solomon code generated in 2 is set to 4 times 8, but if an integer k including 4 is used, (9, 8k)
By generating the Reed-Solomon code, the k parity data PO to Pk-1 are distributively combined bit by bit to the eight 8-bit data to form 9-bit data with just the right amount. be able to.

[Effects of the Invention] As explained above, the present invention generates a Reed-Solomon code having a total length of an integer multiple of 9 for 8-bit data that is an integer multiple of 8 that is aggregated into one block, and The resulting parity data is allocated one bit to the end of each 8-bit data to make 9-bit data, and then these 9-bit data are encoded into 10-bit data whose DSV, which indicates the DC balance of each data, is zero when NRZI encoded. Bit-balanced code or D
Either the main conversion table that converts SV to a positive 10-bit unbalanced code or the secondary conversion table that converts a 10-bit balanced code or DSV to a negative 10-bit unbalanced code is updated every time the conversion is performed. By selecting so that the DSV integrated value converges to zero, converting the code to 10-bit data, and finally performing NRZI encoding, error correction processing is interwoven with the code conversion process, and the 8-bit data is converted into an error correction function and D
1o bit NR that has C-free characteristics and satisfies the RLLC law
Since it can be converted to ZI data and error correction processing is combined with code conversion processing, it is possible to reduce the correction capacity burden of error correction processing that is performed separately from code conversion processing. In code conversion, the DC component of converted data can be suppressed to within ±4, and the maximum code inversion interval can be suppressed to 9.6 times the bit interval. By storing a pair of main and sub conversion tables in a conversion ROM with 2 addresses and adding a table selection circuit, 10-bit data that satisfies the RLLC rule can be obtained. In addition, when used in conjunction with the DPCM (Differential Pulse Code Modulation) method, frequently occurring 8-bit differential data is converted to 10-bit data with zero DSV. Therefore, it is possible to suppress the DC component of the converted data in the normal use range as much as possible.Furthermore, for example, in a magnetic recording and reproducing system, NRZI data can be reproduced using the partial response method, and even if the read data is encoded Excellent effects such as accurate data reproduction can be achieved even when the data is reversed.

[Brief explanation of drawings]

Fig. 1.2 is a circuit configuration diagram showing each embodiment of an 8/10 encoder and decoder to which the 8/10 code conversion method of the present invention is applied, and Figs. FIG. 19 is a circuit configuration diagram showing an example of a conventional 8/I4 encoder. 11,... 8/10 encoder, 12. ．． ．． Error correction processing circuit, 13. ,．． 9/10 conversion circuit, 14°, conversion ROM
, 17. ,,Table selection circuit. 31., decoder, 32. ,．． 10/9 conversion circuit. 33. Error correction processing circuit.

Claims (1)

[Claims] Converting 8-bit data to 10-bit data 8/
10 code conversion methods, 8 that are aggregated into one block
For 8-bit data that is an integer multiple of , a Reed-Solomon code with a total length that is an integer multiple of 9 is generated, and the resulting parity data is distributed one bit at the end of each 8-bit data to generate 9-bit data. and then converts the 9-bit data into a 10-bit balanced code with a zero DSV indicating the DC balance of each data item or a 10-bit unbalanced code with a positive DSV when the 9-bit data is NRZI encoded, or Code conversion to 10-bit data while selecting either a sub-conversion table that converts to a 10-bit balanced code or a 10-bit unbalanced code with negative DSV so that the DSV integrated value updated each time converges to zero. The 8/10 code conversion method is characterized in that the 10-bit data obtained by the code conversion is further NRZI encoded.