JP3013651B2 - Digital modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital
(Run Length Limited) NRZI (Non Retu
More particularly, the present invention relates to a digital modulator for converting a channel code suitable for a recording medium or a transmission path.

[0002]

2. Description of the Related Art Generally, when information is recorded on a recording medium at a high density and reproduced, the frequency band of the recording / reproducing system is limited, so that the data must be modulated so as to be suitable for this band. Various proposals have been made as a method for modulating digital information so as to be suitable for the frequency band of the recording / reproducing system, and NRZI modulation is known as one of the methods.
In this NRZI modulation method, when a bit sequence consisting of bit “0” and bit “1” is input, the level is inverted at bit “1” and not inverted at bit “0”, so this signal is recorded. As a result, inversion of a signal can be recorded as a magnetization reversal on a magnetic recording medium, and can be recorded as a physical shape change on an optical recording medium.

However, with the NRZI modulation method alone, when trying to increase the recording density on a medium, the adjacent magnetization reversal and shape change interfere with each other at the time of reproduction, making it impossible to read accurately. As a method for solving this problem, a method of performing NRZI modulation using an RLL code is known. In this RLL code, the run length of “0” is such that the number of “0” existing between “1” and “1” in the bit sequence is at least d and at most k (> d). Is limited, and when an m-bit input information word is converted into an n-bit RLL code, it is called a (d, k; m, n) code.

In the method of performing NRZI modulation and recording using the RLL code, the bit sequence of the input information is divided into m bits of information, and the appropriate run lengths d to k are selected and encoded into n bits. When the NRZI modulation is performed, the minimum inversion interval Tmin of the recording signal can be extended as compared with the case where the input information is directly NRZI modulated. Therefore, reading errors during reproduction can be reduced, and as a result, the recording density can be increased.

If the recording signal has a low-frequency component on the frequency spectrum, reading becomes difficult depending on the reproduction system. Therefore, it is desirable that the low-frequency component of the recording signal be as small as possible. Here, DS is used to evaluate the low-frequency component of the recording signal.
V (Digital Sum Variation) is used. This DS
V is x when one time slot of the signal is level “1”.
= + 1, x = −1 when the level is “0”, and is the sum of x from the start point of the signal to a certain time. Therefore,
It can be said that the deviation of DSV from "0" is small, and the signal whose DSV changes quickly has little low-frequency component.

Further, as another modulation method, EFM (Eigh
t Fourteen Modulation) is used for a CD (compact disc), and the RLL code is applied. For example, in the EFM modulation method disclosed in Japanese Patent Publication No. 1-27510, n (= 8)
When converting into a (= 14) -bit conversion information word, a code with a limited run length of bit “0” is assigned,
The redundant bit string of nb (= 3) is adaptively determined from the held DSV and sandwiched in the conversion information word, thereby maintaining the RLL coding rule between the conversion information words and reducing the low-frequency component of the modulation signal. Restrained. Therefore, finally m
Each input information word of (= 8) bits is converted into a bit string of n (= 17) bits.

As another conventional modulation method, as shown in Japanese Patent Publication No. 4-77991, a bit "0" is used.
The conversion information word is constructed so that the run length of the conversion information word is maintained at the boundary of the conversion information word, and the CDS (Code Digital
The conversion information word of Sum) = 0 is made to correspond one-to-one with the input information word, and the conversion information word of CDS ≠ 0 has a different CDS sign,
In addition, there is known a method in which conversion information words having different absolute values of the CDS are made to correspond to an input information word as a set to adaptively select the conversion information word and suppress a low-frequency component of a modulation signal.

[0008]

In the method disclosed in Japanese Patent Publication No. 4-77991, the recording density ratio D
R (Density Ratio) = 1.14, and DR = 1.41 in the EFM system, so that the EFM system can record at higher density. In addition, since the servo device and the focus device of the optical disk device use the low-frequency component of the reproduced signal, if the modulation signal itself recorded on the optical disk contains many low-frequency components, the servo and focusing may be incorrectly performed. Become. However, in the EFM system, low-frequency components are suppressed by redundant bits. However, in an optical disc device that performs more accurate servo and focusing, the suppression degree of the EFM system may be insufficient.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a digital modulation device capable of improving the recording density ratio DR and suppressing low-frequency components.

[0010]

According to the present invention, in order to achieve the above object, the minimum number d of "0" between "1" and "1" in a (d, k; m, n) RLL code is set. By increasing the number of redundant bits, the number of n-bit conversion information words is increased,
A plurality of conversion information words are made to correspond to one input information word, and several types of redundant bit strings are added before or after each conversion information word. That is, according to the present invention, the number of “0” s existing between “1” and “1” in the bit sequence in the m-bit input information word input in the cycle is at least d, and at most k bit sequence is converted into an n-bit bit sequence, and this bit sequence is converted into NR
In digital modulation apparatus for ZI modulation, before entered
To convert an m-bit input information word into n-d bits
To, | CDS | and the conversion information word group A of n-d bit ranges continuous in a predetermined "0" before and after the relatively small and converting information words, CDS is relatively large n-d bit and possess the conversion information word group B +, the conversion information word group a, B + of
One of the first bits corresponding to the m-bit input information word
A first table that outputs the converted information word, is branched input
The m-bit input information word is converted to nd bits.
For the conversion information word group A of the first same conversion information word group A of the table of the n-d bit, the first table
Converted information word group B + than CDS is relatively small, and the previous
Serial conversion information word group B + against reverse polarity n-d-bit conversion information word group of B- and closed and, the conversion information word group A, B-
One of the m-bit input information words corresponding to the m-bit input information word.
2 a second table for outputting the conversion information word ,
Add a new bit string to the bit string selected before
Bits selected before this cycle to follow.
Set the subsequent level of the row to "1" or "0" and the period
Output at the time of
Calculates / ranks the subsequent level of the cycle corresponding to the level
And subsequent use level calculation / storage means for paying, before the present period or
Output at the time of the cycle,
By the time of completion, DS up to the cycle corresponding to the above DSV
A DSV storage means for storing V, the first converted by the first and second tables, a plurality of bit string of n bits by adding redundancy bits of d bits each between the second conversion information word a redundant bit addition unit for generating, before
Of the cycle output from the subsequent level calculating / storing means.
Output level from previous DSV storage means
DSV up to the previous cycle and the redundant bit addition
Each of the CDSs corresponding to the plurality of bit strings output from the means
NRZI-modulated D of the plurality of bit strings based on
A DSV calculating means for calculating the SV, and the redundant
In the first and second tables,
The converted first and second converted information words are d and k
It is determined whether or not the coding rule is satisfied.
Selection prohibition signal output means that outputs a selection prohibition signal when
And referring to the result of the selection inhibition signal output means,
Selection means for a plurality of DSV calculated from serial DSV calculating means selects one of the bit sequence closest to "0", one of the bit string selected by said selection means NRZI
Digital modulation apparatus characterized by comprising a means for modulating are provided.

[0011]

According to the present invention, | CDS | is relatively small, and the continuation of "0" before and after the conversion information word is a predetermined range.
When the conversion information word is converted to a d-bit conversion information word, the change in DSV is reduced, and the possibility of selecting whether or not to invert the polarity by the redundant bit before the conversion information word is increased. As a result, the possibility that the increase or decrease of the DSV can be controlled increases, and thus the low-frequency component can be suppressed. Further, when the conversion information word having a relatively large CDS or the conversion information word having a relatively small CDS is converted, the possibility that the increase / decrease of the DSV can be controlled by the redundant bits is not so large, Since the sets are of opposite polarity, the likelihood of being able to control the DSV is increased, and therefore low frequency components can be suppressed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital modulation apparatus according to the present invention, FIG. 2 is an explanatory diagram showing a bit relationship between a redundant bit and a conversion information word before and after it, and FIGS.
FIG. 3 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 1 shows, as an example, "1" in a bit sequence.
The number of “0” existing between “1” and “1” should be at least 2
(= D) and at most 9 (= k), and the input information word of 8 (= m) bits is 17 (= m).
n) Convert to a bit string of bits (2, 9; 8, 17)
A circuit for performing NRZI modulation of this bit string using an RLL code is shown. In this embodiment, since d = 2, an 8-bit input information word is converted into a 15-bit conversion information word, and a 2-bit redundant bit string is inserted between the conversion information words.

This modulation is performed with a period in which an input information sequence of 8 bits is input to the input terminal 1 as one cycle. First, the information sequence input to the input terminal 1 is converted into an 8-bit input information sequence by the shift register 2 and RO
M3a, 3b are applied as addresses, and FIGS.
As shown in (1), two 15-bit conversion information words, which are stored in advance in the ROMs 3a and 3b as the tables "0" and "1" and are composed of nd bits, respectively, are read. In addition,
3 to 11 show that an 8-bit input information sequence is converted into a decimal number.
In other words, a 15-bit conversion information word and its CDS for the input information words "0" to "255" represented by decimal numbers are shown.

[0015] At the end of the two conversion information word, the redundant bit sequence generator 4a, 4b, 4c and generating respective 2-bit redundant bits "00", "01", "10" 1
Added as 7th and 16th bits, ROM3a, 3b,
One of the six types of 17-bit bit strings combined with the redundant bit string generators 4a, 4b, 4c is selected by the selector 5 based on the selection signal from the DSV comparator 17. This bit sequence is converted by the shift register 6 into a bit sequence with the 17-bit higher-order bit at the head, NRZI-modulated by the modulator 8, and output via the output terminal 8.

Here, the tables "0" and "1" stored in the ROMs 3a and 3b will be described. First, in order to suppress the low frequency component of the modulated signal, the DSV of the modulated signal
That is, when one time slot of the signal is at level “1”, x = + 1, and when it is at level “0”, x = −1, and the fluctuation range of the sum of x from the start point of the signal to a certain time is small, and “ It must converge quickly to "0". This is because the CDS (ie, the conversion information word is changed from level “0” to NR)
Achieved by increasing the frequency of occurrence of a conversion information word having a small DSV of a modulation signal in the case of ZI modulation and increasing the chance of controlling the DSV by selecting the type of redundant bit string and the next conversion information word. be able to.

Here, as shown in FIG. 2, when the bit string of the previous conversion information word is "... 1", since d = 2 is restricted by the coding rule, the redundant bit "0" is added at the end.
Only “0” can be added, and there is no DSV control opportunity. In the example shown in FIG. 2, when the redundant bit “00” is added, the bit string “001...” Of the next conversion information word
The run length of “0” is “4”.

Therefore, in this embodiment, as described above, the CD
In order to reduce S and increase the chances of controlling the DSV, the absolute value | CSD | of the CDS should be as small as possible, and the redundant bit string before and after the conversion information word should not be as fixed as possible. The conversion information words of the tables "0" and "1" are determined so that the run length Frun of the part "0" and the run length Rrun of the rear part "0" are both within a predetermined range as much as possible (for example, 2 or more and 5 or less). Have been.
That is, in the present embodiment, the number of redundant bits of the EFM system is changed from "3" to "2", and as a result, two tables are provided. Optimum classification and arrangement are performed for them.

Specifically, since d = 2 and the conversion information word is 15 bits, first, among the conversion information words satisfying this condition, one having a large absolute value | CSD | 347 words are used, except those reserved for. Then, as shown in FIG. 3, in the common conversion information word group A in the tables “0” and “1”, the input information words “0” to “1” of 165 words represented by decimal numbers
64 ", the run length of both front and rear" 0 "is 1
As described above, the conversion information words (“0” to “131”) with CDS of ± 1, ± 3, and ± 5 and the run length of the rear “0” are “0”, but the CDS is small (= ± The conversion information word (1) (“132” to “164”) is assigned.

In the conversion information word group B + in the table “0”, 91 input information words “165” to “25” are input.
For "5", the conversion information word (CD
S = 3, 5, 7, 9) are assigned, and table “1” is assigned.
In the conversion information word group B-, the input information words “165” to
A conversion information word having a relatively small CDS (CDS = 1, -1, -3, -5, -7) is assigned to "255".

Returning to FIG. 1, the two conversion information words read from the ROMs 3a and 3b are respectively used by the polarity determiners 9a and 9b.
b. The polarity determiners 9a and 9b determine "0" when the signal levels of the first bit and the last bit are the same when NRZI modulation is performed only on these two conversion information words, and when they are different, It is determined as “1”.
That is, this polarity determination is equivalent to obtaining an exclusive OR of all bits of the conversion information word. This polarity judging device 9
The polarities determined by a and 9b are selected by the selector 10 based on a table selection signal from the decoder 23. This selected polarity and the main cycle from the decoder 22
Based on the subsequent use level of the modulated signal polarity in the previous cycle of the redundant bit sequence selected by (the period), followed a level of the modulated signal of the period is calculated by the level calculator 20 is stored in the register 21 You. That is, the decoder 2
2 and the output of the selector 10 and the register 21
The exclusive OR with the output is output and stored in register 21.
It is delivered. Here, the subsequent level is explained.
Then, a new bit is added to the bits before the cycle.
To calculate DSV, which will be described later,
In NRZ, the bit sequence selected before the cycle is
When the state of the last bit after I conversion is "1" or "0"
It is necessary to know the status of the
Shall be expressed as Therefore, register 21
Indicates that the subsequent level at the end of the immediately preceding cycle is “1”
Or, output as “0” to the DSV calculator 16 in the cycle.
And by the time the cycle is completed,
And stores the subsequent level of the cycle corresponding to
You. Therefore, the succeeding level that calculates / stores the succeeding level
The level calculating / storing means includes polarity determiners 9a and 9b,
, A level calculator 20, a register 21, a decoder
23. At this time, the above operation is performed.
To be selected by the selector 5 during the cycle.
A control signal for designating one of the ROMs 3a and 3b.
Is supplied to the selector 10 via the decoder 23,
Corresponds to one of the specified ROMs 3a, 3b
One of the polarity determiners 9a and 9b is selected.

The two conversion information words read from the ROMs 3a and 3b are also used as the rear run length measuring devices 11a and 11a, respectively.
11b, the number of consecutive bits "0" on the lower bit side is measured. This measured value is
Data selector 1 based on the table selection signal from
2 and is stored in the register 13.

Further, the two converted information words read from the ROMs 3a and 3b are also input to the front run length measuring devices 14a and 14b, respectively, and the number of consecutive bits "0" on the upper bit side is determined. Measured. Based on these measured values and the run length of the trailing bit “0” stored in the register 13, the run length rule determining units 15 a and 15 b determine the coding rule of d = 2 and k = 9 when redundant bits are added. Is satisfied or not, and if the combination is not satisfied, the selection prohibition signal
It is output to the V comparator 17.

The redundant bits "00", "01",
Based on the six types of 17-bit bit strings to which “10” has been added, the level of the modulation signal held by the register 21, and the DSV of the previous cycle stored in the register 19, the conversion information word is converted in the cycle. D when modulated
The SV is calculated by the DSV calculator 16. These six DSVs are input to both the DSV comparator 17 and the selector 18, and the DSV comparator 17 executes the run length rule determining units 15a and 15d.
When the selection prohibition signal from b is not input, a signal for selecting an information word whose DSV is closest to "0" is output to the selectors 5, 18 and the decoders 22, 23. When the selection prohibition signal is input, the next information word close to "0" is selected.

The DSV immediately after the cycle selected by the selector 18 is stored in the register 19.
Is a DSV calculator 16 for calculating the DSV of the next cycle.
Is applied to The selection signal of the DSV comparator 17 is converted by the decoder 22 into the polarity of the redundant bit string in the same manner as the polarity determination units 9a and 9b and applied to the level detector 20, and is converted by the decoder 23 into a table selection signal. It is applied to selectors 10 and 12.

Therefore, according to the above embodiment, the run length of the front and rear “0” is both 1 or more, and the CDS is ± 1, and
A conversion information word group A to which conversion information words of ± 3 and 5, and a conversion information word in which the run length of the front and rear “0” is “0” but the CDS is small (= ± 1) are assigned. In the case of conversion, the variation of DSV is reduced, and the possibility of selecting whether or not to invert the polarity by the redundant bit before the conversion information word is increased. As a result, the increase or decrease of DSV is controlled. Are more likely to be able to
Low frequency components can be suppressed.

A conversion information word group B + to which a conversion information word having a relatively large CDS (CDS = 3, 5, 7, 9) is assigned, or a conversion information word (CD having a relatively small CDS).
When S = 1, -1, -3, -5, -7) is converted by the assigned conversion information word group B-, there is little possibility that the increase / decrease of the DSV can be controlled by the redundant bits. Although not large, most of the sets of the conversion information word groups B + and B− have opposite polarities, so that the possibility of controlling the DSV increases, and therefore, low frequency components can be suppressed. In the above embodiment, (2,9; 8,17) R
The LL code has been described as an example, but instead, for example, (1,
7; 8, 13) Other coding rules such as RLL codes may be used. In this case, since the redundant bits are 1 (= d) bits and the bit string to be finally converted is 13 bits, the conversion information words of the tables “0” and “1” are 1
It becomes 2 bits.

FIG. 12 shows the EFM method on the horizontal axis (0 to 100 kHz) and the (2, 9; 8, 17) RL of the above embodiment.
The frequency spectrum according to the L code is shown, and as is clear from the figure, the (2,9; 8,17) RLL code has a higher EFM.
Low frequency components can be suppressed compared to the method. Further, since the number of redundant bits is two, there is an effect that the circuit configuration can be reduced.

[0029]

As described above, according to the present invention, |
CDS | is relatively small and "0" before and after the conversion information word
Are converted into an nd-bit conversion information word within a predetermined range, the variation in DSV is reduced, and whether or not the polarity is inverted by a redundant bit before the conversion information word is determined. Since the possibility of selecting is increased, the possibility that the increase or decrease of DSV can be controlled is increased,
Therefore, low frequency components can be suppressed. Also,
When the conversion information word having a relatively large CDS or the conversion information word having a relatively small CDS is converted, the possibility that the increase or decrease of the DSV can be controlled by the redundant bits is not so large, but most of the sets are not. Because of the opposite polarity, D
The possibility that the SV can be controlled increases, and therefore, the low-frequency component can be suppressed. Further, since the number of redundant bits is set to d in the (d, k; m, n) RLL code, it is possible to select from more types of codes and assign them as conversion information words, and to obtain a recording density ratio D of the EFM system.
R can be maintained and low frequency components can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a digital modulation device according to the present invention.

FIG. 2 is an explanatory diagram showing a bit relationship between a redundant bit and a conversion information word before and after the redundant bit.

FIG. 3 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 4 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 5 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 6 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 7 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 8 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 9 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG.

FIG. 10 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG. 1;

FIG. 11 is an explanatory diagram showing a conversion table stored in a ROM shown in FIG. 1;

FIG. 12 shows the EFM method and (2, 9; 8, 1) of this embodiment.
7) is an explanatory diagram showing a frequency spectrum of a low-frequency component based on the RLL code.

[Explanation of symbols]

 2, 6 shift register 3a, 3b ROM (conversion table) 4a, 4b, 4c redundant bit string generator 5, 10, 12, 18 selector 7 NRZI modulator 9a, 9b polarity determiner 11a, 11b rear run length measuring device 13, 19, 21 Registers 14a, 14b Front run length measuring device 15a, 15b Run length rule determiner 16 DSV calculator 17 DSV comparator 22, 23 Decoder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/14

Claims (1)

(57) [Claims] An m-bit input information word input in the cycle has at least d, and at most k, 0s existing between "1" and "1" in the bit sequence. Is converted to an n-bit bit string, and this bit string is converted to NR
In the digital modulation device for performing ZI modulation, the input m-bit input information word is converted into nd bits.
To convert, | CDS | and the conversion information word group A of n-d bit ranges continuous in a predetermined "0" before and after the relatively small and converting information words, CDS is relatively large n- d
And possess the conversion information word group of bits B +, the conversion information words
Corresponds to the m-bit input information word from groups A and B +
A first table for outputting one first conversion information word , and n-d bits of the m-bit input information words that have been branched and input.
To convert the bets, conversion information word of said first table
And conversion information word group A of the same n-d bit and the group A, the first conversion information word group table B + than CDS is relatively small, and n of the opposite polarity to the conversion information word group B + −
conversion information word group of d bits B- and closed and said conversion information
Corresponds to the m-bit input information word from word groups A and B-
A second table for outputting one converted second conversion information word, and a new one for the bit string selected before the cycle.
Select before the cycle to follow the bit sequence
The subsequent level of the bit sequence is set to "1" or "0".
Output during the cycle and until the cycle is completed.
The subsequent level of the cycle corresponding to the subsequent level
And a level calculating / storing means for calculating / storing the DSV, and outputting the DSV up to the previous cycle in the cycle.
By the time the cycle is completed, the DSV
DSV storage means for storing DSVs up to a cycle, and the DSV storage means converted by the first and second tables .
Redundant bit adding means for adding d redundant bits between the first and second conversion information words to generate a plurality of n-bit bit strings, and the cycle output from the subsequent level calculating / storing means
From the DSV storage means and the subsequent level up to
DSV up to the previous cycle and the redundant bit
Each CDS corresponding to a plurality of bit strings output from the adding means
DSV calculating means for respectively calculating the NRZI-modulated DSV of the plurality of bit strings based on the first and second bit strings, and the first and second DSVs when the redundant bit is added.
The first and second conversion information words converted by the table are
It is determined whether or not the sign rules of d and k are satisfied.
Selection prohibition signal that outputs a selection prohibition signal when not
And signal output means, with reference to the result of the selection inhibition signal output means, the D
NRZ selection means, one of the bit string selected by said selecting means in which a plurality of DSV calculated from SV calculation means selects one of the bit sequence closest to "0"
Digital modulation apparatus characterized by comprising a means for I modulation.