JPH07245565A - Signal modulating method and signal modulation circuit - Google Patents

Abstract

PURPOSE:To properly suppress a low frequency component by effectively implementing digital sum variation(DSV) control even when the number of margin bits is decreased to increase the recording density. CONSTITUTION:When margin bits M1, M2,...Mm used to connect each word of modulated data are selected, number NI1 of inhibit patterns as to the margin bit M1 selected at present is checked to discriminate whether or not plural patterns are to be selected (step S2). When the plural patterns cannot be selected, the sole margin bit pattern not inhibited is outputted as the M1 (step S3). When the plural patterns are selected, the DSV of the data up to just before a first margin bit Mn for plural-pattern selection is calculated among the margin bits M1, M2,...Mm is calculated and the margin bit pattern minimizing the absolute value of the accumulated DSV is outputted as the M1 (steps S4-S7).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital audio signal,
The present invention relates to a signal modulation method and a signal modulation circuit circuit used when recording a digital video signal, a digital data signal, etc., and can be applied to a read-only optical disc mastering device, a write-once or rewritable optical disc recording / reproducing device, and the like. The present invention relates to a signal modulation method and a signal modulation circuit.

[0002]

2. Description of the Related Art When recording a digital signal such as digital audio, video or data on a recording medium, the digital signal is supplied to a modulation circuit after being added with an error detection / correction code and is suitable for the characteristics of a recording / reproducing system. Is converted into a different code (channel coding).

Here, an outline of a signal format of, for example, a so-called compact disc (CD) system is as follows. That is, the sampling frequency is 44.1 kHz, the number of quantization is 16 bits (straight line), the modulation method is the EFM channel bit rate, 4.3218 Mb / s, the error correction method is the CIRC data transmission rate, 2.034 Mb / s, and the modulation method is 8-14 conversion or EFM
Is used.

As shown in Table 1 below, the EFM converts an input 8-bit code (hereinafter referred to as a symbol) into a 14-channel bit code, a 24-channel bit synchronization signal and a 14-channel bit subcode. After adding
This is a modulation method in which these codes are connected by margin bits of 3 channel bits and NRZI recording is performed.

[0005]

[Table 1]

FIG. 11 is a diagram showing the frame structure of the CD system. As shown in FIG. 11, one sync frame (6 sample value intervals, 6 samples for each of the L and R channels,
The data (music signal) of 24 symbols and the parity of 8 symbols that are input from the CIRC (Cross Interleaved Reed-Solomon Code) encoder to the modulation circuit during the period of 1 sample is 16 channel data are converted into 14 channel bits respectively and 3 channel bits , And the NRZI recording is performed on the disc at a channel bit rate of 4.3218 Mbps.

Each symbol input to the modulation circuit has a channel bit pattern in which the number of "0s" between "1" and "1" is 2 or more and 10 or less by referring to a look-up table ROM, for example. Each is converted. The channel bit pattern of the frame synchronization signal Sf is “10000.
0000001000000000010 ", and the margin bit patterns are" 000 "," 001 "," 0 ".
One of 10 "and" 100 "is selected.
The sub-coding frame consists of 98 frames,
The subcode sync signal S0 (= “0010000000000000) as the subcode of the 0th and 1st frames.
1 ”), S1 (=“ 00000000010010 ”)
Is added (see FIG. 12).

FIG. 13 shows a channel bit pattern after EFM and a DSV for one example of sample values of input data.
It is a figure which shows (digital thumb variation).

One 16-bit sample is divided into high-order 8 bits and low-order 8 bits, which are input to a modulation circuit via a CIRC encoder and 8-14 converted to 1 respectively.
It is an information bit of 4 channel bits. As described above, two or more and ten or less "0" s are interposed between the information bits "1" and "1". "000", "001" as margin bits,
One of “010” and “100” is selected, and this rule is always established even for the connection portion of information bits, and 17 channel bits (however, 27 channel bits in the case of the frame synchronization signal Sf). ) Is used as the EFM signal from the modulation circuit 4.3.
It is output at 218 Mbps.

As described above, since two or more and ten or less channel bits "0" are interposed between any channel bit "1" and the next channel bit "1", the high level or low level of the NRZI recording waveform is obtained. The level duration (recording wavelength) is always 3 T or more and 11 T or less (see FIG. 13).

In this case, the shortest recording wavelength is 3T and the longest recording wavelength is 11T. T is the channel clock 4.321
One cycle is 8 MHz, and this is hereinafter referred to as the 3T to 11T rule of the EFM modulation rule.

Consider DSV as an index of the DC balance of the NRZI recording waveform. DSV is given as the time integral of the recording waveform. That is, the amount of change in DSV when the high level of the recording waveform continues for the unit time T is set to +1 and
The change amount of DSV when the low level continues for the unit time T is set to -1.

The change with time of DSV when the initial value of DSV at time t ₀ is assumed to be zero is shown in the bottom row of FIG. Here, the modulated signal in the periods t _{1 to} t ₂ has a 17-channel bit pattern “010000010”.
It is not uniquely determined by 00001001 ″, and is the modulation signal level at time t ₁ , that is, the final level of the modulation signal waveform in the period t _{0 to} t ₁ (hereinafter,
CWLL).

[0014] Thus, the modulation signal waveform shown is the time t ₀
CWLL is a case of a low level (CWLL = "0"), the modulation signal waveform when the CWLL = "1" (high level) at time t ₀ is reversed pattern replacing the high level and low level at.

Similarly, the increase / decrease of DSV also depends on the above CWLL, and when CWLL = "0" at time t ₀ , the information bit pattern "0100010010".
Change in DSV due to 0010 "(hereinafter referred to as 14NWD), that is, DSV in the period t _{0 to} t ₀ +14
The change amount of is +2 as shown in FIG. Contrary to the figure, if CWLL = "1" at time t ₀ , 14NWD
= -2. Further, the amount of change in DSV during the period t ₀ +14 to t ₁ +14 is referred to as 17NWD.

Next, the margin bits inserted in the period t ₀ +14 to t ₁ will be described. Four types of margin bits “000”, “001”, “010” and “10”
Among the 0's, "001" and "100" cannot be inserted, and "010" or "000" can be inserted according to the 3T to 11T rule of the above-mentioned modulation rule. If the number of "0" s at the end of the information bit pattern of B is B and the number of "0s" at the tip of the current information bit pattern to be output later is A, then B = 1 and A = 1. The leading edge of the bit must be “0” and the trailing edge must be “0”, and the insertable margin bit pattern is “0X0.” Here, X represents don't care.

At the bottom of FIG. 13, the solid line shows the DSV when "010" is inserted as the margin bit, and the broken line shows the DSV when "000" is inserted.

In general, when inserting a margin bit at a certain connection point, it is necessary to select one that satisfies the 3T to 11T rule of the above modulation rule. Also, it is necessary to prohibit the occurrence of a two-time repeated pattern of 11T, which is the same as the frame synchronization pattern, by inserting the margin bit.

When margin bits satisfying these rules are inserted, the accumulated DSV up to that point is inserted.
In addition, the margin bit and the cumulative DSV up to the end of the next information bit pattern are obtained, and the one having the smallest absolute value is selected as the optimum margin bit.

The margin bit obtained by such an algorithm satisfies the 3T to 11T rule of the above-mentioned modulation rule even at the connecting portion of two 14-bit data, prevents the erroneous occurrence of the frame sync signal, and also the EFM. The cumulative DSV of the signal is as close to zero as possible.

[0021]

By the way, the conventional EF
In the method M, the shortest run length is limited to 2. Therefore, it is sufficient that the margin bit is 2 bits in order to satisfy only the limitation such as the run length. If the margin bit can be reduced to 2 bits, the data recording density can be reduced to (1) without changing the physical size such as the recording wavelength.
7/16) times can be improved.

However, there are only three types of 2-bit margin bits, and it is often the case that only one type of margin bit can be inserted due to restrictions such as run length. Therefore, in the conventional DSV control method, DSV
There are many uncontrollable sections, and as a result, the low-frequency component of the modulation signal is not sufficiently suppressed, which adversely affects the stability of servo and the error rate during data demodulation.

The present invention has been made in view of such circumstances, and a signal modulation method and a signal modulation that can effectively perform DSV control when margin bits are selected and can appropriately suppress low frequency components. It is to provide a circuit. In particular, when improving the data recording density by reducing the number of margin bits, it is possible to reduce the adverse effect on the DSV control due to the narrow selection range of the margin bits, and to sufficiently suppress low frequency components. It is an object of the present invention to provide a signal modulation method and a signal modulation circuit that can be performed by.

[0024]

In order to solve the above-mentioned problems, in the signal modulation method according to the present invention, each i-bit code sequence to be input is j (where i, j is an integer, i> j) channels. Converting to a bit pattern, a margin bit that suppresses the low frequency component of the recording waveform is selected from the selectable margin bits that satisfy a predetermined modulation rule among a plurality of types of margin bits, and the j-channel bit pattern Is a signal modulation method for combining the selectable margin bits, the margin bit is selected when the selectable margin bit is unique, and when there are two or more selectable margin bits, digital sums of channel bit patterns continuous to these are selected. The variation (DSV) is calculated respectively, and when the next selectable margin bit is unique, the calculation range is further Spread, to calculate the range until just before the selectable margin bits is 2 or more, selected and used margin bit absolute value of the cumulative DSV is minimized.

Specifically, between one word or one word of information data D ₁ and the next one word of data D _{2 in the} j channel bit pattern sequence, among the plurality of types of margin bits, When selecting from selectable margin bits satisfying the modulation rule and combining them, each information data following the data D ₂ is sequentially set as D ₃ , D ₄ , D ₅ ... When there are two or more, the data D between the above data D ₂ and D ₃ for a finite integer m
_{Between 3} and D ₄ , ..., Selectable margin bits at each connection point between data D _m and D _{m + 1} The number of selectable margin bits is checked, and selection is possible at any connection point. N = m when the number of margin bits is single
If there is a connection point having two or more selectable margin bits, the first connection point is data D _n and D.
_{n + 1,} and the data D ₁ and the data D ₂ of the next word are combined at each of two or more selectable margin bits, and the data D ₂ to the data D _n of each information data are combined. A digital sum variation obtained by combining each of them with a single selectable margin bit is calculated, and added to the cumulative digital sum variation before the data D ₁ to calculate a cumulative digital sum variation up to the data D _n. Select and use the margin bit that minimizes.

Here, it is preferable that the integer m giving the upper limit value of the word for calculating the digital sum variation is 3 or more.

When the modulation rule is such that the length j of the converted channel bit pattern is fixed and the shortest run length is limited to d, a margin bit used for coupling between channel bits is set. It is preferably d bits.

Further, in the above modulation, the input 8-bit code sequence is converted into a 14-channel bit pattern.
The -14 modulation is adopted, and in this case, it is preferable that the number of the margin bits is 2.

Next, in the signal modulation circuit according to the present invention, the input i-bit code sequence is j (where i, j
Is an integer, i> j) channel bit patterns are converted, and between these j channel bit patterns, a margin bit that satisfies a predetermined modulation rule and suppresses a low frequency component of a recording waveform is selected from a plurality of types of margin bits. And a signal modulation circuit for combining the same, in which one word data D ₁ having the j-channel bit pattern sequence and the next one word (one word)
When combining with the data D _{2 of}
Each word following the above data D ₂ and subsequent words is sequentially D ₃ , D
₄ , D _5, ... For a finite integer m, between D ₁ and D ₂ , between D ₂ and D ₃ , between D ₃ and D ₄ , ..., D With respect to the margin bit at each point between _m and D _{m + 1} , a prohibition margin bit discriminating means for discriminating a pattern prohibited by the above-mentioned modulation rule and outputting the discrimination information, and an output from this prohibition margin bit discriminating means , Data D ₁ , D ₂ , ..., D _m , D _{m + 1} of each word of the j channel bit pattern, a signal relating to the final waveform level of the margin bit preceding D ₁ , and A signal representing the magnitude of the accumulated digital sum variation immediately before D ₁ is inputted, and a margin bit generating means for generating an optimum one of the plurality of types of margin bits is provided, thereby solving the above problem. .

Also in the case of this signal modulation circuit, the integer m giving the upper limit of the word for calculating the digital sum variation is set to 3 or more, and the length j of the converted channel bit pattern is fixed. , When the shortest run length is limited to d, the margin bit used for coupling between channel bits is d bits, and
It is preferable to adopt 8-14 modulation for the above-mentioned modulation and to set the number of margin bits to 2.

[0031]

According to the above construction, when the margin bits to be inserted can be selected in two or more kinds due to the restriction by the modulation rule such as run length, the connection point up to the next in which two or more kinds of margin bits can be selected. By selecting a value that minimizes the absolute value of the cumulative DSV of, the information of the section where DSV control is not possible in the conventional method is also reflected in the DSV control, and the low frequency component of the modulated signal Suppression will be carried out appropriately.

In the case of concrete implementation, the upper limit of the DSV calculation range is limited to a finite section, and when a connection point where two or more types of margin bits can be selected is not found in this section, Is the cumulative DSV within the finite section
By selecting a margin bit that minimizes the absolute value of, it is possible to prevent the DSV calculation range from becoming extremely wide and the amount of calculation to become enormous, which is practical. It is effective to set this finite section to 3 words or more.

Further, by converting the information portion by 8-14 conversion, so-called EFM, which has been conventionally adopted in so-called CD, and reducing the margin bit from 3 bits in the conventional method to 2 bits, the conventional modulation circuit IC and The demodulation circuit IC can be used almost as it is, and the data recording density can be increased by (17/16) times while suppressing the low frequency component.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION A signal modulation system and circuit according to the present invention each input an i-bit code sequence to j (where i, j
Is an integer, i> j) is converted to a channel bit pattern, and the j channel bit patterns are assumed to be connected by a plurality of types of margin bits. Some types of margin bits may be prohibited when combined with j-channel bit data due to restrictions of modulation rules such as longest and shortest run lengths, and selectable margin bits other than the prohibited margin bits. It is necessary to select the margin bit that suppresses the low frequency component of the recording waveform from among the above.

The suppression of the low frequency component is realized by selecting a margin bit that minimizes the absolute value of the cumulative digital sum variation (hereinafter referred to as DSV). The calculation range of this DSV is The DSV calculation range is expanded according to the number of selectable types of the margin bits from the next onward without limiting to the position immediately before the next margin bit as in the conventional case. That is, with respect to the margin bit arranged between the data of two words or j channel bits of two words, when the selectable margin bit is unique, the margin bit is selected and used. When there are two or more selectable margin bits, D of the channel bit pattern consecutive to them is
SV is calculated respectively, and when the next selectable margin bit is unique, the calculation range is further expanded, and the range until just before the selectable margin bit becomes 2 or more is calculated, and the absolute value of the cumulative DSV is calculated. The smallest margin bit is selected and used.

This is because the number of types of margin bits is small and the above-mentioned modulation rule is violated when the data is combined with j channel bits, especially when the number of margin bits is reduced to increase the recording density. This is because the number of unselectable margin bits that cannot be controlled by DSV is increased, and the calculation of the above DSV is started from the margin bit having two or more selectable margin bits. By calculating the range up to the margin bit in which the selectable margin bit is 2 or more through the margin bit in which the selectable margin bit is uniquely limited, the information of the section in which the DSV control is impossible is also changed to the DSV control. Thus, the low frequency component of the modulation signal is effectively suppressed.

In the realization, in order to prevent an endless search from a connection point currently selecting a margin bit to a connection point at which two or more types of margin bits can be selected next, this search range Alternatively, if the DSV calculation range is limited within a finite interval, and if no more than the following two types of connection points that can be selected are found within this finite interval, the margin bit currently selected is accumulated at the end of this finite interval. Select a margin bit that minimizes the DSV.

Preferred embodiments of the present invention will be described below with reference to the drawings. Digital audio signal,
When recording a digital video signal, a digital data signal, etc., the digital signal is added with an error detection / correction code and then supplied to a modulation circuit and converted into a code suitable for the characteristics of the recording / reproducing system (channel coding). .

First, FIG. 1 is a flow chart for explaining an algorithm for selecting an optimum margin bit as a main part of an embodiment of a signal modulation system according to the present invention. The optimum margin bit in this case is such that the cumulative DSV among the selectable margin bits that do not violate the modulation rule when combined with the channel bit pattern is as close to 0 as possible.

In the embodiment shown in FIG.
It is assumed that the word length i of the input data is 8, the word length j of the converted channel bit pattern is 14, that is, 8-14 conversion, and the margin bit is 2 bits. An example of the output signal thus modulated is shown in FIG.
Shown in.

In this embodiment, one word data D _{1 of the} 14-channel bit pattern sequence and the next 1
Margin bit M for coupling with word data D _2
The case where the optimum one is selected from the above-mentioned plural kinds of margin bits is shown as 1, and the words following the word D ₂ and subsequent words are sequentially set as D ₃ , D ₄ , ... And checked up to D _{m + 1.} ing. Further, the margin bit of the connection point between the data D ₂ and D ₃ is M ₂ , the margin bit of the connection point between the data D ₃ and D ₄ is M ₃ , ..., D _m and D _{m + 1.} The margin bit of the connection point between and is M _m .

The specific contents of each step in FIG. 1 will be described later. As a schematic operation in the flowchart of FIG. 1, is it possible to select a plurality of margin bits for the current connection point in step S2? If it is determined that only one can be selected, the process proceeds to step S3, and if two or more can be selected, the process proceeds to step S4 and thereafter. At step S4 to S7, the finite integer m, the margin bit of the connection points M _2, M _3, ··
Check the number of selectable or not prohibited margin bits for M _m ,
When there is only one selectable margin bit at any connection point, n = m + 1 is set, and when there is a connection point having two or more selectable margin bits, the first connection point is D _n and D _{n. +1} and combining D ₁ and D ₂ with two or more of each of the selectable margin bits, and each of the words from D ₂ to D _n with a single selectable margin bit. Calculate the digital sum variation (DSV) of the combined ones, and accumulate D before D ₁ above.
The cumulative DSV up to D _n is calculated by adding it to SV, and a margin bit that minimizes the absolute value is selected and output as M ₁ .

Prior to the detailed description of FIG. 1, preferred fields of application and modulation signal formats of this embodiment will be described.

That is, this embodiment is particularly preferable when applied to modulation when recording signals such as digital audio, video and data on a high density optical disc. The outline of the signal format in this high-density optical disc is as follows, for example. That is, the modulation method is a type of 8-14 conversion, the channel bit rate is 24.4314 Mbps, the error correction method is the CIRC data transmission rate of 12.216 Mbps, and the modulation method is a type of 8-14 conversion as described later.

The modulation method used this time is based on the conversion table shown in Table 1, which is the same as the EFM that has been conventionally used for so-called compact discs (CDs) and the like, and the input 8-bit code (hereinafter referred to as symbol) is used for 14 channels. This is a modulation method in which a NRZI recording is performed after converting into a bit code, adding a synchronization signal of 24 channel bits and a subcode of 14 channel bits, and connecting these codes with a margin bit of 2 channel bits.

FIG. 3 is a diagram showing a frame structure of a recording signal obtained by being modulated by the modulation method in the high density optical disc, and FIG. 4 is a diagram showing a sub-coding frame structure.

24 symbol data (music signal, video signal, digital data, etc.) and 8 symbol data input from a CIRC (Cross Interleaved Reed-Solomon Code) encoder to a modulation circuit (neither shown) in one sync frame period. Parity is converted into 14 channel bits and concatenated with margin bits of 2 channel bits. As shown in FIG.
54 channel bits, and NR on the above high density optical disc at a channel bit rate of 24.4314 Mbps.
ZI recorded.

For each symbol input to the modulation circuit (not shown), for example, referring to a look-up table ROM, the number of “0” s between “1” and “1” is 2 or more and 1 or more.
Each channel bit pattern is converted into 0 or less. The channel bit pattern of the frame synchronization signal Sf is “10000000000100000000001”.
0 "and the margin bit pattern is" 00 ",
One of "01" and "10" is selected. 1
The sub-coding frame consists of 98 frames,
The subcode sync signal S0 (= “0010000000000000) as the subcode of the 0th and 1st frames.
1 ”), S1 (=“ 00000000010010 ”)
Is added (see FIG. 4).

FIG. 5 is a diagram showing a channel bit pattern and DSV (digital sum variation) after being modulated by the 8-14 conversion which is the modulation method of the present embodiment, for one example of input data.

In FIG. 5, 8-bit unit data is input to a modulation circuit via a CIRC encoder (not shown), and is 8-14 converted into information bits. As described above, two or more and ten or less "0" s are interposed between the information bits "1" and "1". "00" as the margin bit,
One of "01" and "10" is selected so that this rule is always established even at the connection between information bits, and 16 channel bits (however, 26 channel bits in the case of the frame synchronization signal Sf). ) As a unit, a modulation signal from a modulation circuit (not shown)
It is output at 4.4314 Mbps.

As described above, since two or more and ten or less channel bits "0" are present between any channel bit "1" and the next channel bit "1", the high level or low level of the NRZI recording waveform is obtained. The duration of the level (recording wavelength) is always 3T or more and 11T or less.

In this case, T is the channel clock 24.4.
One cycle is 314 MHz, the shortest recording wavelength is 3T and the longest recording wavelength is 11T. Hereinafter, this is referred to as the 3T to 11T rule of the modulation rule of this embodiment.

Digital sum variation (DSV) is used as an index of direct current (DC) balance of the NRZI recording waveform.
think of. DSV is given as the time integral of the recording waveform. That is, the change amount of the DSV when the high level of the recording waveform continues for the unit time T is set to +1 and the change amount of the DSV when the low level continues for the unit time T is set to -1.
And

The change with time of DSV when the initial value of DSV at time t ₀ is assumed to be zero is shown in the bottom row of FIG. Here, the modulated signal in the period t _{1 to} t ₂ is 1
6-channel bit pattern "01000000100000
It is not uniquely determined by 0100 ″, but depends on the modulation signal level at time t ₁ , that is, the final level (hereinafter, referred to as CWLL) of the modulation signal waveform in the period t _{0 to} t ₁ .

[0055] Thus, the modulation signal waveform shown in FIG. 5, CWLL is high level at time t ₀ (CWLL =
“1”), and CWLL = at time t ₀
The modulated signal waveform in the case of "0" (low level) has an inverse pattern in which the high level and the low level are replaced.

Similarly, the increase / decrease of DSV also depends on the above CWLL, and when CWLL = "1" at time t ₀ , the information bit pattern "1000100001".
Change in DSV due to "000010" (hereinafter 14NW
D), that is, the DSV in the period t _{0 to} t ₀ +14
The change amount of is -4 as shown in FIG. Contrary to the figure, if CWLL = "0" at time t ₀ , 14NWD
= + 4.

Next, the margin bits inserted in the period t ₀ +14 to t ₁ will be described. Among the three types of margin bits “00”, “01” and “10”, “01” cannot be inserted and “10” or “00” can be inserted according to the 3T to 11T rules of the above-mentioned modulation rule. That is, if the number of "0s" at the end of the previous information bit pattern output before the margin bit is B and the number of "0s" at the tip of the current information bit pattern output later is A, Since B = 4 and A = 1, the leading edge of the margin bit may be either “0” or “1”, but the trailing edge must be “0”, and the insertable margin bit pattern is “X0”. Become. This X indicates an arbitrary (Don't care) value.

In FIG. 5, "10" is set as the margin bit.
The solid line shows the DSV when "" is inserted, and the dotted line shows the DSV when "00" is inserted.

Generally, when a margin bit is inserted at a certain connection point or connection point, 3T to 11T of the above modulation rule is inserted.
You have to choose one that meets the rules.

Further, it is also necessary to prohibit the occurrence of the twice repeated pattern of 11T, which is the same as the frame synchronization pattern, due to the insertion of the margin bit. This prohibition rule is "1 at the connection point" for the simplification of the algorithm.
Even if it is expanded, it does not prevent the system from being established.

FIG. 6 is a diagram showing the determination of the prohibited margin bit (hereinafter referred to as _Minh ) based on the above rule. Two
The margin bits to be inserted between the four 14-bit data D ₁ and D ₂ are tested on the bits shown by hatching in FIG. 6, and D ₁ and D
_The margin bit M _inh which should not be used for concatenation of ₂ is determined.

The algorithm for determining the prohibited pattern is as follows.

(1) When the total of the number A of "0" s at the front end of the 14-bit data D ₂ and the number B of "0s" at the end of D ₁ is 8 or more (A + B ≧ 8): In this case Margin bit "00" is prohibited in (M _inh = “0
0 ").

(2) When the most significant bit C1 of the 14-bit data D ₂ is "1" (A = 0) or the next most significant bit C2 is "1" (A = 1): The margin bit "01" is prohibited. (M _inh = “01”).

(3) When the least significant bit C14 of the 14-bit data D ₁ is "1" (B = 0) or the next most significant bit C13 is "1" (B = 1): The margin bit "10" is prohibited. (M _inh = “10”).

The operation shown in FIG. 1 is performed based on the modulation rule and the prohibited pattern discrimination as described above. That is, FIG. 1 shows a margin bit M for coupling the 14-channel bit data D ₁ and the next data D ₂ shown in FIG.
FIG. 6 is a diagram showing an algorithm for selecting an optimum margin bit for ₁ . The optimum margin bit referred to here is one that does not conflict with the above-mentioned prohibition margin bit and that makes the accumulated DSV as close to zero as possible.

In the first step S1 in FIG. 1, for each of the margin bits M ₁ , M ₂ , ..., M _m , the data D ₁ , D ₂ , D of each word of the 14-channel bit pattern sequence is written. _{3, ···, D m, D} m + 1 inhibited margin bit pattern to break the 3T~11T rule of the modulation rule when bound to _M inh1, M inh2,
..., _Minhm, and the number of prohibited patterns NI
₁ , NI ₂ , ..., NI _m are calculated.

In the next step S2, it is determined whether or not the selectable margin bit is unique by checking the number NI ₁ of the prohibited patterns of the currently selected margin bit M ₁ . Specifically, if there are two prohibited patterns among the three types of margin bits “00”, “01”, and “10”, only one selectable margin bit is present. It is determined whether or not NI ₁ = 2.

If YES in step S2, that is, if the number NI _{1 of} prohibited patterns is 2 and it is determined that there is only one selectable margin bit, the process proceeds to step S3. In this case, since the margin bit M ₁ has no choice, the unprohibited pattern of M ₁ is output as it is and the process is terminated.

If NO in step S2, that is, if the number NI _{1 of} prohibited patterns is less than 2 and there are two or more selectable margin bits, there is room for selection with respect to the margin bit M _1. S
Proceeding to step 4 and after, margin bits for suppressing low frequency components are selected.

That is, in step S4, 2 ≦ n ≦ m
For n of n, the minimum n such that NI _n <2 is obtained. NI _n = 2 for all n with 2 ≦ n ≦ m,
That is, when there is no choice for all M _n ,
Let n = m + 1.

In the next step S5, D ₂ to D _n of the 14-bit data are connected with a non-inhibited margin bit pattern, that is, a unique selectable margin bit pattern.

In the next step S6, with respect to the margin bit M ₁ currently selected, when the 14-bit data D ₁ and D _{2 and} after are connected by a selectable margin bit pattern that does not correspond to the prohibition pattern M _inh1 , The cumulative DSV up to D _n is calculated, including That is,
For each pattern in which the margin bit M ₁ is not prohibited, the cumulative DSV up to D _n is calculated including the amount before D ₁ .

In the next step S7, the above step S6 is executed.
A margin bit pattern is output so that the absolute value of the cumulative DSV calculated in step 1 is minimized. That is, the pattern of M ₁ that gives the cumulative DSV with the smallest absolute value is output, and the process ends.

FIG. 7 is a diagram for explaining an example of the case where the finite integer m that gives the upper limit value of the maximum concatenation number of the 14-channel bit word or the word in the range for calculating the DSV is 3. Is.

In FIG. 7, 14-bit data D ₁
At the start of, CWLL = "0" and cumulative DSV =-
Suppose it was 3. In the case of the example of FIG. 7, D ₁ and D
_At the connection point of ₂ , any of the margin bits "10", "01", and "00" can be selected (NI ₁ =
0). At the connection point of D ₂ and D ₃ , margin bits other than “00” cannot be selected (NI ₂ = 2), and D ₃ and D ₄
"10" and "01" can be selected at the connection point of (NI ₃
= 1). Wherein each pattern of margin bit M ₁ "1
Channel bit patterns corresponding to 0 "," 01 ", and" 00 "are shown in FIGS. 7A, 7B, and 7C, respectively, and the DSV locus is shown in each curve of FIG. 7D. a, b,
Each is shown in c.

When the conventional margin bit determination algorithm is applied, the accumulated DSVs at the end of D ₂ are compared, and “01” that minimizes the absolute value becomes the optimum margin bit of M ₁ .

According to the method of this embodiment, M ₁ is selected so that the cumulative DSV up to D ₃ is minimized. From these, it is determined that "00" is the optimum margin bit.

Next, FIG. 8 shows a low frequency component of a recording waveform generated by using the optimum margin bit determining algorithm of this embodiment by FFT (Fast Fourier Transform) to determine the optimum margin bit determining algorithm of the conventional method. Is applied to the margin bit of 2 bits and shows a comparison with the low frequency component. Here, m = 4. The sampling frequency of the FFT is the channel clock frequency, and the horizontal axis of the graph shows the Nyquist frequency, that is, the frequency normalized by (sampling frequency) / 2. When the present method is used, even if the margin bit is 2 bits, the signal power is suppressed by about 6 dB in the vicinity of the normalized frequency = 0.0005, compared with the case where the margin bit is 2 bits in the conventional method. It is shown. The normalized frequency of around 0.0005 corresponds to around 6 kHz when the above-mentioned high-density optical disk format is adopted, and it can be seen that the adoption of this embodiment can greatly contribute to stabilization of the pickup servo.

Next, FIG. 9 shows an embodiment of the signal modulation circuit according to the present invention. In this embodiment, the DSV
It shows a case where the integer m that gives the upper limit of the number of words of 14-channel bit data when calculating is 4 is set.
In the prohibition margin bit discriminating circuit 30 and the margin bit generating circuit 50 of FIG. 9, operations similar to those of the above-described embodiment of the signal modulation method are performed.

In FIG. 9, data of 32 symbols per sync frame is input to the input terminal 10 from a data generating circuit (not shown). Each 8-bit symbol is stored in the table 1 by the table ROM 11.
As described above, 8-14 conversion is performed on 14-bit data.

Constructing a Sub-coding Frame 98
The 0th and 1st sync frames of the sync frame include
As described above, the 14-bit subcode sync signals S0 and S1 are added. This subcode sync signal S0
And S1 are added based on a sub-code sync timing signal (not shown).
Done by

The pseudo frame sync adding circuit 13 is based on a frame sync timing signal (not shown), and the 14-bit pseudo frame sync signal S'f (= "1XXXX
XXXXXXXXX 10 ") is added to the head of each sync frame. The bit pattern of the leading 1 bit and the trailing 2 bits of the pseudo frame sync signal S'f is a regular 24-bit frame sync signal (=" 100000000001).
Since it is the same as that of (000000000010 "), when the margin bit is selected, the same processing as other 14-bit data becomes possible.

14-bit data including the subcode sync signals S0 and S1 and the pseudo frame sync signal S'f are supplied to the registers 14 to 17 connected in cascade.
The input of the register 14 is D _5, and the outputs of the registers 14 to 17 are D ₄ , D ₃ , D ₂ and D ₁ .

The 14-bit data D ₅ and D ₄ are supplied to the inhibition margin bit discrimination circuit 30. Also, D ₅
Is also supplied to a margin bit generation circuit 50 described later.

The prohibition margin bit discriminating circuit 30 outputs D ₄
At the connection point of D ₅ and D ₅ , a prohibited margin bit that conflicts with the above-mentioned prohibited margin bit determination algorithm is determined
A margin bit inhibit signal S _inh4 is generated. Specifically, the combination of bits described with reference to FIG. 6 can be realized by detecting the combination determination circuit.

The margin bit inhibit signal S _inh4 consists of 3 bits, and each bit has three types of margin bits “1”.
0 "," 01 "and" 00 "respectively. For example, when the first and second margin bits" 10 "and" 01 "are prohibited by the above-mentioned prohibition margin bit discrimination algorithm, 3 margin bits Prohibition signal S
_inh4 is set to "110".

The frame sync conversion circuit 18 converts the pseudo frame sync signal S'f of the sequentially input 14-bit data D ₁ into a regular 24-bit frame sync signal Sf based on a frame sync timing (not shown). The other 14-bit data is supplied to the P / S register 19 as it is.

The 24-bit parallel-in / serial-out (P / S) register 19 will be described later as 14-bit data (24-bit data only for the frame sync signal Sf) based on the channel bit clock of 24.4314 MHz. The 2-bit data (margin bit) input from the margin bit generation circuit 50 is serially output alternately.

The serial signal output at a speed of 24.4314 Mbps is NRZI-modulated by the NRZI circuit 20 and then supplied as a recording signal to, for example, a master disc mastering device of a read-only optical disc or a disc recording circuit of a write-once / rewritable optical disc. It

DS to which NRZI modulated signal is supplied
The V integration circuit 70 integrates the DC component of this input signal in units of 16 channel bits and outputs the value of this cumulative DSV to the margin bit generation circuit 50.

Next, the margin bit generation circuit 50 will be described. The margin bit generation circuit 50 outputs the optimum margin bit among the three types of margin bits “10”, “01”, and “00”. The optimum margin bit means that the two 14-bit data D ₁ and D ₂ described above are connected by this margin bit so that 3T to 11 which is the above-mentioned modulation rule at the connection point.
This is a margin bit selected so that the T rule is satisfied, the erroneous occurrence of the frame sync signal is prevented, and the cumulative DSV of the modulated output signal is as close to zero as possible.

The margin bit generation circuit 50 realizes the optimum margin bit selection algorithm described above with reference to FIG. Margin bit generation circuit 5
A specific configuration example of 0 is shown in FIG.

The margin bit inhibit signal S _inh4 indicating the inhibit margin bit is connected in cascade with the detection circuit 51 for detecting whether there is only one selectable margin bit, that is, whether the number of inhibit patterns is 2. The first of the three registered registers 55, 56, 57,
And the subsequent DSV calculation circuit 58.

In the present embodiment, the margin bit inhibit signal is uniquely determined by the combination of two 14-bit data by the inhibit margin bit discrimination algorithm described above. Therefore, the margin bit inhibit signal S indicating the inhibit margin bit at the connection point of the data D ₄ and D _5
inh4 is delayed by synchronizing with the flow of data,
The margin bit inhibit signal S _inh3 at the connection point of D ₃ and D ₄ can be used as it is.

Therefore, the output of the register 55 is the margin bit inhibit signal S _inh3 , the output of the register 56 is the margin bit inhibit signal S _inh2 , and the output of the register 57 is the margin bit inhibit signal S _inh1 . Margin bit inhibit signal S
_inh3 and S _inh2 are supplied to the subsequent DSV calculation circuit 58, and the margin bit inhibition signal S _inh1 is supplied to the optimum margin bit determination circuit 68 described later.

The detection circuit 51 is a circuit which outputs "1" from the prohibition signal S _{inh4 when} a plurality of margin bits M ₄ cannot be selected, and outputs "0" otherwise. In this circuit, the 3 bits of the inhibit signal S _inh4 is “11”.
It can be realized by detecting using a combinational circuit that any of 0 ”,“ 101 ”, and“ 011 ”is detected.The output of the detection circuit 51 is NS ₄ .

The detection output NS ₄ is supplied to the decoder 54 and also to the first register 53 of the registers 53, 52 connected in cascade. The detection output NS ₄ can also be NS ₃ or NS ₂ as it is due to a delay, like the prohibition signal S _inh4 . Therefore, the register 53,
The outputs from the register 52 are NS ₃ and NS ₂ , respectively, and these are also supplied to the decoder 54, respectively.

The decoder 54 receives each detection output N
This is a circuit that obtains a range in which a subsequent DSV calculation circuit 58, which will be described later, obtains a DSV from S ₂ , NS ₃ , and NS ₄ . As signals indicating this DSV calculation range, DE ₂ , DE ₃ , D
A signal DE consisting of 4 bits of E ₄ and DE ₅ is output.
Each bit of this output signal DE, DE ₂ , DE ₃ , DE ₄ ,
DE ₅ is 14-bit data D ₂ , D ₃ ,
It means that 14-bit data corresponding to D ₄ and D ₅ and corresponding to the bit for which “1” is set is added to the calculation of the subsequent DSV. The output signal DE is the circuit 54 of FIG.
It is obtained from the psychological table described in the block.

The 14-bit data D ₅ input to the margin bit generation circuit of FIG. 10 is supplied to the 14-bit DSV calculation circuit 63. The 14-bit DSV calculation circuit 63 has the above C when the 14-bit data D ₅ is started.
WLL, that is, assuming that the final level of the modulation signal waveform or the level immediately before the start is “0”, calculates the DSV of the 14-bit data D _{5 and} sets the value to 14
It is output as NWD ₅ . This is realized by converting 14-bit data D ₅ into NRZI in the circuit, obtaining the number of “1” and the number of “0”, and subtracting them. This value is represented in the form of 5 bit 2's complement.

The 14-bit DSV calculation circuit 63 also sets 1
When the CWLL at the start of the 4-bit data D ₅ is “0”, the CWLL at the end of the 14-bit data D ₅ is also obtained, and this is output as LL ₅ .

The respective output signals 14NWD ₅ , LL ₅ from the 14-bit DSV calculation circuit 63 are sent to the first register 64 of the cascade-connected registers 64-67 and the first register 59 of the cascade-connected registers 59-62. Each is supplied. The outputs from the registers 64 to 67 become 14 NWD _{4 to} 14 NWD ₁ , respectively, and the respective registers 59 to 59
The fact that the outputs from ˜62 are respectively LL _{4 to} LL ₁ is clear from the same consideration as in the case of the signal S _inh4 . Signal 14NWD ₂ ~14NWD ₅ and the signal LL ₂ ~LL ₅ are both supplied to the subsequent DSV calculating circuit 58. The signal 14NWD ₁ and the signal LL ₁ are
Both are supplied to the optimum margin bit discrimination circuit 68.

Each signal S _{inh2 to} S _inh4 , DE, 14NWD
_{2 to} 14 NWD ₅ and LL _{2 to} LL ₅ are input to the subsequent D
The SV calculation circuit 58 calculates the DSV in the range of the input calculation range designating signal DE, assuming that CWLL at the start point of the 14-bit data D ₂ is “0”.

To calculate the subsequent DSV, basically, the DSVs of the 14-bit data and the margin bits may be cumulatively added.

The margin bit pattern has a DSV which is “10” → + 2 “01” → 0 “00” → −2, assuming that CWLL at each start time is “0”. Regarding the CWLL for the next connected data, "00" is the CWLL for the margin bit, and "10" and "01" are the inverted CWLL for the margin bit.

When performing the addition, it should be noted that the sign reversal of the DSV may occur due to the CWLL at the connection point.

For example, DE = “1100”: Calculate DSV up to D ₃ S _inh2 = “110”: M ₂ is allowed only “00” 14NWD ₂ = + 2, LL ₂ = “1” 14NWD ₃ = -4 Think about the case.

Since LL ₂ = “1” and M ₂ is “00”, CWL is set for the margin bit and D _3.
L is "1", DSV of margin bit and 14 NW
Sign inversion occurs for D ₃ . Therefore, (subsequent DSV) = 2 + (− 1) × (−2) + (− 1) ×
(-4) = 8.

In this way, the DSV of the pattern following the 14-bit data D _{2 and} thereafter is calculated, and the subsequent DSV
Is supplied to the optimum margin bit discrimination circuit 68.

The optimum margin bit discriminating circuit 68 receives the 14-bit data D for the inhibition signal S _inh1 , the subsequent DSV, LL ₁ , 14NWD ₁ , the accumulated DSV and the input of CWLL.
_The optimum margin bit M ₁ that connects ₁ and D ₂ is output.

As the optimum margin bit, the inhibit signal S
If there is only one selectable margin bit pattern that is not prohibited by _inh1 , that margin bit pattern is output.

When there are a plurality of selectable margin bit patterns which are not prohibited, the DSV when the 14-bit data D ₁ and D ₂ are connected by each is the same as in the case of the subsequent DSV calculation circuit 58 described above. The total DSV is obtained by carrying out the calculation while paying attention to the calculation and further performing the same addition as the cumulative DSV. The absolute value of the total DSV corresponding to each margin bit pattern is calculated, and the margin bit pattern having the smallest value is output as the optimum margin bit pattern M ₁ .

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, a system in which the margin bit is 2 bits was considered, but even in a system in which the margin bit is 3 bits as in the conventional CD, there is only one option of the margin bit depending on the input data. Since the limitation may occur, the low frequency component suppressing effect can be obtained by applying the present invention. Further, the present invention is not limited to the application to the 8-14 conversion, and the same effect can be expected in other modulation methods in which data is connected by margin bits.
Further, the frame structure, the sub-coding frame structure, etc. described in the above embodiments do not give essential limitations in the implementation of the present invention, and it is needless to say that they can be applied to a system having another data structure. is there.

[0114]

As described above, according to the present invention,
Of the multiple types of margin bits, a selectable margin bit that suppresses the low-frequency component of the recording waveform is selected from the selectable margin bits that satisfy a predetermined modulation rule, and the selectable margin described above is used when combining the channel bit patterns. When there are two or more bits, the digital sum variation (DS
V) is calculated respectively, and when the next selectable margin bit is unique, the calculation range is further expanded, and the range until just before the selectable margin bit becomes 2 or more is calculated, and the absolute value of the cumulative DSV is calculated. Since the smallest margin bit is selected, DSV cannot be sufficiently controlled by the conventional DSV control method. Even in a system in which margin bit options are often limited, margin bit options are generated. Since the control is performed so as to reduce the cumulative DSV in consideration of the DSV, a great effect can be obtained in suppressing the low frequency component of the modulation signal.

Therefore, when the number of margin bits is reduced to increase the density of the optical disc, it is possible to greatly contribute to stabilization of servo and reduction of error rate during data demodulation, which is preferable.

In the concrete implementation, if the upper limit of the DSV calculation range is limited to a finite section and no connection point that allows selection of two or more types of margin bits is found within this section, Is the cumulative DSV within the finite section
By selecting a margin bit that minimizes the absolute value of, it is possible to prevent the calculation range of DSV from being extremely widened and the amount of calculation to be huge, so that there is no practical problem. It is effective to set this finite section to 3 words or more.

Further, the information data portion is converted by 8-14 conversion, so-called EFM, which has been conventionally adopted in so-called CD, and the margin bit for connection between 14 channel bits is reduced from the conventional 3 bits to 2 bits. As a result, the modulation circuit IC, the demodulation circuit IC, etc., which have been widely used and supplied at low cost, can be used as they are, which is economically advantageous, while realizing suppression of low frequency components. Data recording density (17
/ 16) can be increased by a factor of 16).

[Brief description of drawings]

FIG. 1 is a flowchart for explaining an optimum margin bit selecting operation which is a main part of one embodiment of the present invention.

FIG. 2 is a diagram showing a connection between data of a modulation output signal and a margin bit.

FIG. 3 is a diagram showing a frame structure of a modulated output signal.

FIG. 4 is a diagram showing a sub-coding frame structure of a modulated output signal.

FIG. 5 is a diagram showing input data and an 8-14 modulated waveform.

FIG. 6 is a diagram showing discrimination of prohibited margin bits.

FIG. 7 is a diagram showing a relationship between selected margin bits and digital thumb variations.

FIG. 8 is a diagram showing an effect of suppressing low frequency components.

FIG. 9 is a block diagram showing a schematic configuration of a signal modulation circuit according to an embodiment of the present invention.

FIG. 10 is a block diagram showing a specific configuration example of a margin bit generation circuit.

FIG. 11 is a diagram showing a frame structure of a conventional modulated output signal.

FIG. 12 is a diagram showing a conventional sub-coding frame structure of a modulated output signal.

FIG. 13 is a diagram showing a conventional sampled value and an EFM modulation waveform.

[Explanation of symbols]

 30 Prohibited Margin Bit Discriminating Circuit 50 Margin Bit Generating Circuit 51 Margin Bit Unselectable Detection Circuit 54 Decoder for Determining Subsequent DSV Calculation Range 58 Subsequent DSV Calculation Circuit 63 14-bit DSV Calculation Circuit 68 Optimal Margin Bit Discrimination Circuit

Claims (7)

[Claims] 1. The input i-bit code sequence is j
(However, i and j are integers, i> j) are converted into channel bit patterns, and between these j channel bit patterns, from among selectable margin bits satisfying a predetermined modulation rule among a plurality of types of margin bits, A signal modulation method for selecting and combining margin bits for suppressing low-frequency components of a recording waveform. When the selectable margin bit is unique, the margin bit is selected, and there are two or more selectable margin bits. When I do it,
Calculate the digital sum variation of the channel bit pattern that continues to these, further expand the calculation range when the next selectable margin bit is unique, and calculate the range up to immediately before the selectable margin bit becomes 2 or more. The signal modulation method is characterized by selecting and using the margin bit that minimizes the absolute value of the accumulated digital sum variation. 2. A selection between one word data D _{1 of the} j-channel bit pattern sequence and the next one word data D ₂ of the plurality of types of margin bits satisfying the modulation rule can be selected. When the margin bits are selected and combined, the words following the data D ₂ and subsequent words are sequentially transferred to D ₃ and D.
_4, and D ₅ · · ·, if the selectable margin bits if only the use that margin bits, present the selectable margin bit is 2 or more, for a finite integer m, and the D ₂ between D _3, between D ₃ and D _4, ···, examine each selectable number of margin bits for margin bit of each point between the D _m and D _{m + 1,} any point Also, in the case where the number of selectable margin bits is single, n = m + 1 is set, and when there is a point having two or more selectable margin bits, the first point is between D _n and D _{n + 1} , A digital sum variation of D ₁ and D ₂ combined with each of two or more selectable margin bits, and each word from D ₂ to D _n combined with a single selectable margin bit. Before D ₁ above 2. The signal modulation according to claim 1, wherein the accumulated digital sum variation up to D _n is obtained by adding the accumulated digital sum variation to the accumulated digital sum variation, and a margin bit whose absolute value is minimum is selected and used. Method. 3. The signal modulation method according to claim 2, wherein the integer m giving an upper limit value of a word for calculating the digital sum variation is 3 or more. 4. When the modulation rule is such that the length j of the converted channel bit pattern is fixed and the shortest run length is limited to d, a margin bit used for coupling between channel bits is 3. The structure according to claim 1, wherein the structure is composed of d bits.
The described signal modulation method. 5. The signal modulation method according to claim 1, wherein the modulation employs 8-14 modulation for converting an input 8-bit code sequence into a 14-channel bit pattern. 6. The signal modulation method according to claim 5, wherein the number of margin bits is two. 7. The input i-bit code sequence is j
(However, i and j are integers, i> j) Channel bit pattern
Converted to multiple types of margin bits,
A marker that satisfies the modulation rule and suppresses the low-frequency component of the recorded waveform.
Select the desired bit and select the above j-channel bit pattern.
A signal modulation circuit for coupling between, wherein one-word data having the above j-channel bit pattern sequence
D₁And the next one word data D₂Margin bit between
The above data D₂Each word that follows after
Sequentially₃, D_Four, D_Five・ ・ ・, Where finite integer
For m, the above D₁And D₂Between D₂And D₃With
Meanwhile, D₃And D_FourBetween ..._mAnd D _{m + 1}Between
The margin bit of each point is prohibited by the above modulation rule.
Prohibition of discriminating the pattern to be stopped and outputting the discrimination information
Margin bit discriminating means, an output from the prohibiting margin bit discriminating means, and the above j
Data D of each word of channel bit pattern₁, D₂,
.., D_m, D_{m + 1}And above D₁Margin to be prefixed to
The signal related to the final waveform level of the bit and the above D₁Immediately before
A signal representing the magnitude of the cumulative digital sum variation of
Input and, and select the most
Margin bit generating means for generating an appropriate one
A signal modulation circuit characterized by the above.