KR100424483B1 - Method and apparatus of converting a series of data words into a modulated signal - Google Patents

Abstract

The present invention relates to a method of converting a series of data words into a modulated signal. An apparatus for performing this method adds r bits of different digital words to an input data word to generate a plurality of selection sequences, and to generate the selected plurality of selection sequences at a predetermined m / n coding rate. Accordingly, r is modulated into a sequence meeting a predetermined (d, k) condition, and the low frequency suppression characteristic for the modulated (d, k) condition matching sequences is 25 dB or more, and an average coding rate is 0.53 or more. Means for using the values of and k, and measuring the undesired degree of the modulated (d, k) condition matching sequences and thus selecting one (d, k) condition matching sequence for recording on the record carrier. By including a means for structuring, the maximum DC component suppression and the maximum coding rate can be obtained by appropriately selecting the modulation conditions of r and k.

Description

Method and apparatus of converting a series of data words into a modulated signal

The present invention relates to a data modulation method for suppressing a DC component while complying with a preset (d, k) code regulation.

2. Description of related technology

Run length restriction codes, generally denoted as (d, k) codes, have been widely and successfully applied to modern magnetic and optical recording systems. The codes and means for implementing the codes are , Codes for Mass Data Storage Systems "(ISBN 90-74249-23-X, 1999), described in detail by KA Schouhamer Immink.

The runlength restriction code is an extension of the initial non return to zero (NRZ) code, where zeros written in binary indicate no (magnetic flux) change in the recording medium, whereas binary 1 ( Ones indicate that the magnetic flux has shifted from one direction to the other in the recording medium.

In the above (d, k) code, in addition to the above-described recording rule, at least '0' must be added between d consecutive data '1' by 'd', and '0' between consecutive data '1'. There is an additional condition that at least d must exist and k must not exceed. The first condition is for eliminating interference between symbols generated by a group of pulses to be reproduced when a series of '1's are continuously recorded. The second condition is for reproducing data by locking the PLL to the transition of the reproduction signal. To recover the clock from.

If the string of consecutive '0's in which' 1 'is not interleaved is too long, the clock reproduction PLL is out of sync.

For example, the (1,7) code must have at least one '0' between the '1's recorded and no more than seven consecutive' 0s' between the '1s' recorded. do. A series of encoded bit strings is converted into a modulated signal consisting of bit cells having a high or low signal value through modulo-2 integration, in which the modulated signal is converted. Bit '1' represents a change from high to low, or vice versa, and bit '0' represents no change in the modulation signal.

In addition, the minimum inversion time Tmin, which can be expressed as (d + 1) T, is equal to 2T corresponding to two times T of a one-bit time interval in the recording waveform, and can be represented by (k + 1) T. The maximum inversion time Tmax is equal to 8T corresponding to eight times the bit time interval T.

On the other hand, in the channel bit string generated by the (1,7) code, the minimum inversion time Tmin appears more frequently than the inversion times such as 3T and 4T. Many edge information appearing at short intervals, such as 2T and 3T, is advantageous for the generation of the clock signal in many cases.

However, as the recording density of the recording medium increases, the minimum inversion time Tmin becomes a problem, which is that if the minimum length of 2T occurs continuously in the recording waveform, the waveform is more likely to be distorted. . This is because the output size of the 2T waveform is relatively smaller than the output size of other waveforms, which is easily influenced by factors such as defocus and horizontal tilt.

Furthermore, when the minimum mark 2T is continuously recorded at a high linear density, the disturbances such as noise are more easily affected, so that errors are easily generated even in the data reproduction operation.

In such a case, since the error pattern in data reproduction appears in many cases as the front and rear ends of the minimum mark edge Edge are shifted, the length of the bit error is increased.

When data is transmitted through the transmission line or recorded on the recording medium, as described above, the data is modulated into a code sequence suitable for the transmission line or the recording medium before transmission or recording. If a DC component is included in the modulated code sequence, various error signals such as tracking errors generated in the servo control of the disk driver may be shifted or jitter may be easily generated.

Therefore, a signal without direct current component should be used because the first reason is that the recording channels typically do not respond to low frequency components. Suppressing low frequency components in a signal is an optical recording in which the signal is recorded in a track. This works very advantageously when reading signals from the medium, as it allows the continuous tracking control to be unobstructed by the recording signal.

And, by sufficiently suppressing low frequency components, it is possible to perform improved tracking in which audible noise is reduced. For these various reasons, it is desirable to make a lot of effort to ensure that the modulated sequence does not contain direct current components as much as possible.

As a method for preventing the DC component from being included in the modulated sequence, a DSV (Digital Sum Value) control method has already been proposed. The DSV is a total value obtained by adding a bit string value to the bit string as a result of NRZI modulation of the channel bit string, with 1 assigned to +1 and 0 assigned to -1. It becomes an indicator indicating a direct current component.

If the value for which you are calculating the DSV is virtually constant, it means that the low frequency component is not included in the frequency spectrum of the signal. DSV control is generally not applied to sequences generated by standard (d, k) codes. DSV control for the standard (d, k) code is achieved by calculating the DSV of the encoded bit string after being modulated for a set time and inserting a preset number of DSV control bits into the encoded bit string. At this time, in order to improve the code efficiency, it is preferable to select the number of the DSV control bits as small as possible.

Advantageously, the encoded signal comprises a sequence of q codewords, and inserts a synchronization signal between the encoded signal portions, wherein the synchronization signal should not be generated within the sequence of encoded signals. do.

Typically, the sync pattern consists of two bits of logical '0' containing k consecutive bits larger than k, or k bit lengths separated by logical '1'. That is, two consecutive K length '0' sequences.

On the other hand, the use of such a sync pattern has a disadvantage in that the signal length becomes relatively long and the recording efficiency is lowered. Therefore, it is preferable to use a short sync pattern in which '0' includes two or more consecutive sequences. Do.

An example of using such a signal for recording and reading to an optical or magneto-optical recording medium is described in US Pat. No. 4,501,000, which describes an EFM (Eight to Fourteen Modulation) modulation scheme for recording information on a CD or MD. The EFM modulated signal is obtained by modulating an 8-bit information word into a 14-bit codeword. Three consecutive merging words are inserted between consecutive codewords.

Each 14 bit codeword is between two consecutive '1's. At least two (d = 2) and at least ten (k = 10) '0's must be satisfied. To satisfy this condition, three bit merging words are used between the codewords. do.

The 3-bit merging word will use only four 3-bit merging words, 001,010,000,100, out of the eight possible (= 2 ³ ) merging words, which is the remaining four 3-bit merging words "111", "011". This is because "101" and "110" violate the condition of d = 2.

In the four available merging words, a bit string obtained by concatenating several selectable codewords and merging words satisfies the condition (d, k), and in the corresponding modulo 2 integral signal, the value of DSV is In fact, one is selected that allows the constant to be maintained. When the merging word is selected in this manner, it is possible to minimize the low frequency components in the modulated signal.

On the other hand, the 3-bit merging word selection is selected based on the condition that the channel signal (d, k) must be satisfied without the direct current component present in the channel signal, and the decoding of the EFM signal is very simple. Do. The sync pattern is multiplexed between 33 17-bit strings (3-bit merging word and 14-bit codeword). The 27-bit sync pattern used for the CD format includes 10 consecutive ' It consists of two bit strings of 0's.

The selection of the merging word prevents the synchronization pattern from occurring in the output sequence. In the above recording format, the frequency of the relative synchronization pattern is 4.6% since it is 27 bits out of a total of 588 bits. The decoder ignores the 3-bit merging word and converts the 14-bit codeword into an 8-bit information byte by using a look-up table or a programmable logic array (PLA).

Information recording has a steady need for reading and increasing the writing speed. However, in order to increase the recording speed, a high servo band width of the tracking mechanism is required, which in turn requires satisfying more stringent restrictions that the low frequency component of the recording signal should be limited.

Improvements to suppressing low frequency components also have the advantage of reducing the generation of audible noise from the tracking mechanisms, and therefore, research and development are required to ensure that the modulated signal does not contain low frequency components.

The present invention suppresses direct current components in recording data while complying with a preset (d, k) code regulation, and records a data code of a sequence in which the string of '0's is not long and the minimum d run length is not long. To provide a coding system to

Another object of the present invention is to provide a method and an apparatus for converting a series of data words into modulation signals using low frequency suppression characteristics and modulation conditions capable of improving a coding rate. .

1 shows a block diagram of an embodiment of a coding system according to the present invention,

FIG. 2 illustrates a schematic diagram of some embodiments of a coding structure that performs scrambling and augmenting of a digital word.

3 illustrates a configuration of a selector used in a coding system according to the present invention.

4 shows a block diagram for explaining a method for determining a selectable sequence;

5A and 5B are graphs obtained by experimentally obtaining a low frequency suppression characteristic and a coding rate of a recording signal that can be obtained according to the number of augmenting bits and the maximum run length.

6 shows a configuration of a demodulation device for demodulating a recorded sequence into data words according to the present invention.

※ Explanation of code for main part of drawing

40: Augmentor 42: Scrambler

50: Encoder 52: Judge

54: selector 101: synchronous detector

102: decoder 103: de-scrambler

104: remover

In order to achieve the above object, an apparatus for converting a series of data words into a modulated signal includes generating a plurality of selection sequences by adding different digital words of r bits to an input data word, The generated plurality of selection sequences are modulated into a sequence meeting a predetermined (d, k) condition according to a predetermined m / n coding ratio, and low frequency for the modulated (d, k) condition matching sequences. Means for using values of r and k such that the suppression characteristic is greater than 25 dB and the average coding rate is greater than or equal to 0.53, and the undesired extent of the modulated (d, k) condition matching sequences is measured accordingly And means for selecting one (d, k) condition matching sequence for recording.

1 shows a block diagram of an encoding system according to an embodiment of the present invention, wherein the coding system uses a generator 20 and a selector 22 to generate user data 19, (d, k Is converted into a sequence 23 that satisfies the condition. At this time, a plurality of sub-sequences (Sub Sequence) defined in advance are completely excluded or have a low probability in the converted sequence 23. The (d, k) conditionalized sequence is converted into a run length limited sequence 25 in which low frequency components are suppressed by the precoder 24.

As shown in FIG. 1, the coding system has a generator 20 having a detailed block shown in FIG. 2, and the generator 20 has a data word for each data word 19 and a corresponding block. An augmentor 40 is included that generates multiple intermediate sequences 41 by combining different digital words together. The intermediate sequence 41 is simply created by placing a digital word in front of the data word 19.

The digital word can also be placed after or in the middle of the data word.

The generator 20 also includes a scrambler 42 that alternately scrambles the intermediate sequence 41 to form a select set of various selectable sequences 21. The inclusion of different digital words in the intermediate sequence 41 preferably has the effect that the self-synchronized scrambler 42 is initialized by each intermediate sequence 41 having a different digital word. Therefore, the selection sequence 21 becomes data having relatively good randomness with respect to one data word 19.

Preferably, the augmenter 40 generates 2 ^r intermediate sequences 41 for each data word 19 by combining all possible digital words of length r with the data word 19. In this way, the selection set of selection sequences 21 results in optimal randomization.

3 shows a detailed configuration of the selector 22. The selector 22 comprises a (d, k) encoder 50, which (d, k) encoder 50 assigns each selection sequence 21 to the (d, k) condition matching sequence 51. To. To this end, the selection sequence 21 is partitioned into q m bit length words, which are converted into q n bit length words by the (d, k) encoder. Where n is greater than m and the (d, k) encoder 50 has parameters m = 2, n = 3, d = 1, k = 7, otherwise m = 1, n = 2, d = 2, k Can be a standard type with = 7.

Preferably, in order to increase the encoding efficiency, the encoder 50 is m = 9, n = 13, d = 1 or m = 11, n = 16, d = 1, or m = 13, n = 19, d It may have a parameter defined as = 1, the content of which is described in the unpublished PCT application number PCT / KR00 / 01292 (US application Ser. No. 09 / 707,947). In addition, the encoder 50 may have parameters defined as m = 6, n = 11, d = 2 or m = 11, n = 20, d = 2 or m = 7, n = 13, d = 2. This is also described in PCT application number PCT / KR01 / 00359, which has not yet been published.

The selector 22 includes, for each selectable (d, k) conditional matching sequence 51, a sync pattern, a string with zero '0's, or a string with a long run of alternating Tmin. Means 52 are included for determining if the same unwanted subsequence is included, and if such an unwanted subsequence is detected, the judging circuit is associated with the corresponding undesired subsequence. Penalties, or deductions, are calculated.

The selector 22 also contains, for each selectable (d, k) conditional matching sequence 51, an undesired negative, such as a sync pattern, a string with long '0's, or a string with a long run of variation Tmin. Means 52 for determining the frequency of the sequence and the degree to which the selected sequence 21 contributes to the low frequency component are included.

According to the penalty algorithm rule, the judging means 52 gives low points for the preferred sequence, high points for the undesired sequence, and the selector 22 has the lowest (d, k) condition. Means 54 for selecting a matching sequence are also included.

Fig. 4 shows a block diagram for explaining a general method used for determining and selecting the lowest deductible selectable (d, k) conditional matching sequence 51 according to the present invention. Reference numeral 52 includes a plurality of calculators, each calculator comprising a '0' run length determination 60, a generation of a preset synchronization pattern 62, a variable Tmin run length 64, and a low frequency content. Each of 66 is measured in parallel.

The '0' runlength is used as a measure of successive '0's (generally referred to as' 0' runlengths) detected in one selectable (d, k) conditional matching sequence 51. As one can see, if the sequence continues with a '0' for a long period of time, recording characteristics such as Pit and Land become very long, which leads to a defect that frequently causes tracking errors and errors. Deduction is given according to the '0' run length.

The Tmin calculator 64 measures the number of run lengths of consecutive Tmins, and this Tmin calculator 64 is the shortest T (Tmin) ('01' in the case of d = 1, and in the case of d = 2). , '001') excludes sequences that are repeated too many times. For example, 0101010101 ?? Or 001001001001 ?? A flag is set in the sequence such as to be excluded from the selection means 54 at the rear end. The constraint on the number of repetitive Tmins is referred to as a maximum transition run (MTR) condition.

The synchronization calculator 62 detects whether there is a predetermined synchronization pattern in the selectable (d, k) condition matching sequence 51. When the synchronization pattern is actually detected, the synchronization calculator 12 Will display a flag to identify it in its (d, k) condition sequence, and vice versa.

In addition, the calculator 66 measures the low frequency content of the selectable (d, k) conditional matching sequence 51, and in a preferred embodiment of the present invention the calculator 66 is pre-coded. The device modulates the selectable (d, k) conditional matching sequence 51 and then measures the DSV of the sequence. In this case, preferably, when the sequence becomes a relatively long sequence exceeding 100 bits, the dispersion of the DSV, which is a more suitable measurement method, is measured.

Thereafter, several measured values measured as described above and a flag displayed by the synchronization detection are input to the selection means 54. The selecting means 54 determines the last sequence to be selected and recorded based on the weights associated with the input several measurements. At this time, the sequence having the flag set by the determination means 52 of the front end is excluded from the selection and one is selected from the remaining (d, k) condition matching sequences. In a preferred embodiment of the present invention, a synchronization pattern composed of '0' runs shorter than k may be used. As a result, an advantage of coding efficiency due to a relatively short synchronization pattern can be obtained.

The (d, k) condition matching sequence 51 selected by the selection means 54 is converted into a modulated signal through an NRZI precoding process, which is shifted at '1' and '0'. Is generated from the selected (d, k) conditional matching sequence integrated into two modules with no transitions, and then recorded on the recording medium by conventional recording methods.

Meanwhile, according to the present invention, a method of generating a set of (d, k) conditional matching sequences by adding a digital word of r bits to an input data word and selecting and writing one of them, wherein the length of the digital word r and The following describes how to select the value of the maximum run length k when the minimum run length d is determined.

5A is a result of a simulation of a low frequency suppression characteristic and a coding rate according to the values of r and k when d = 2. In the graph of FIG. 5A, the lower the value of the low frequency suppression characteristic, the better the low frequency characteristic, and the low frequency characteristic and the coding rate are inversely proportional.

In selecting a code set for normal modulation, low frequency characteristics should have better than -25dB, and higher coding rates are advantageous. The higher the coding rate, the more information can be recorded on the recording medium.

Therefore, in the method for selecting and recording one of the various (d, k) condition matching sequences according to the present invention, a graph passing through a region (the colored region 200 in FIG. 5A) having -25 dB or less and a coding rate of 0.53 or more is shown. The decision can be made on the values of r and k. The conditions of (k, r) that satisfy this condition are (10,5), (10,8), (11,5), (11,8), (12,5), (12,8), and the like. .

By the way, when the values of d and k are determined, it has been proved that the maximum low frequency suppression characteristic and the coding rate which can be obtained by selecting the code set under the conditions are already limited. In the graph of FIG. 5A, the graph 'G1' is a maximum boundary graph limited when k = 12, and the graph 'G2' is a boundary graph limited when k = 10.

Therefore, preferably, a value of k whose boundary is limited in a high coding rate and a good low frequency suppression characteristic region is determined, and then a value of r which has a graph approaching the maximum boundary graph determined accordingly is selected. That is, in the simulation result of FIG. 5A, k = 12 and r are determined to have a value of 8. However, if the value of r is large, the number of types of digital words increases, the number of registers corresponding to hardware increases, and the complexity of hardware increases, so the low frequency suppression characteristic of 25 dB or more and the average coding rate of 0.53 or more are selected. It is also possible to select other appropriate values from the value of r to obtain.

In the graph of Fig. 5A, when using the existing EFMCC code, the coding rate is 0.522 at -25dB, but in the case of the present invention which adds r-bit digital words, it is weak in the embodiment where k = 10 and r = 5. It can be seen that a coding rate of 0.532 can be obtained. The coding rate at this time is an average coding rate calculated by adding a digital word to reflect the addition. Thus, a capacity increase of about 2% can be achieved compared to the -25dB EFMCC code.

FIG. 5B shows the results of the simulation of the low frequency suppression characteristics and the coding ratios, fixed at r = 5 when d = 1, and corresponding to k values.

All k, 8, 9, 10, and 11 form a graph that passes through the region 200 with a coding rate of 0.53 and a low frequency suppression characteristic better than 25 dB. Therefore, as the (k, r) condition, (8,5), (9,5), (10,5), and (11,5) can be used for the data modulation recording method according to the present invention.

When the low frequency suppression characteristic is set to 26 dB, the conventional (1,7) PP method has a coding rate of about 0.659, whereas the method of the present invention having (k, r) = (8,5) is about 0.673, which is 2.1. It can be seen from the experimental results of FIG. 5B that a dose increase of% can be obtained, and that (k, r) = (11,5) can result in a dose increase of almost 4%.

On the other hand, the data modulated and recorded as described above is performed by a demodulation device which performs the above-described method in reverse, that is, sequentially performs decoding, de-scrambling, and r-bit digital word removal. Can be restored to the original input data word.

A configuration diagram thereof is shown in FIG. 6. In FIG. 6, the sync detector 101 detects and excludes a sync signal added to a sequence (frame size: (A + r) * m / n bits + sync bits) reproduced from a recording medium (d, k) The conditional reproduction sequence 23 (frame size: (A + r) * m / n bits) is applied to the decoder 102. The decoder 102 outputs a frame of (A + r) bits by performing n / m demodulation which inversely modulates m / n. The descrambler 103 restores a frame of (A + r) bits to a sequence before scrambling, and the augment remover 104 removes r bits of digital words inserted at the front, rear, or middle of the descrambled sequence. This outputs the original data word 19 (A bit) before writing.

As mentioned above, preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art can improve and change various other embodiments within the spirit and technical scope of the present invention disclosed in the appended claims below. , Replacement or addition would be possible.

The method and apparatus for converting a series of data words according to the present invention as described above into a modulated signal, the string of '0' is not long, at least d run, while complying with a predefined (d, k) code specification In recording data codes of sequences having a low length on an information recording medium such as an optical or magneto-optical disc, it is possible to obtain maximum DC component suppression and maximum coding rate.

Claims (16)

Generating a plurality of selection sequences by adding different digital words to an input data word; Modulating the plurality of selection sequences into a sequence meeting a predetermined (d, k) condition according to a predetermined m / n coding ratio; And In the modulated (d, k) conditional matching sequence, a presence of a synchronization pattern, a string of zero consecutive sequences, or a string of long runs of variation Tmin is measured and thus recorded on the recording medium. And selecting one (d, k) condition matching sequence for the number of bits r of the digital word and k, the maximum run length condition, that matches the modulated (d, k) condition. A method of converting a series of data words into a modulated signal, characterized in that the low frequency suppression characteristic for the sequences is greater than 25 dB and the average coding rate is set to be greater than 0.53. The method of claim 1, wherein the predetermined condition k is 10 or more and r is 5 or more. 3. The method of claim 2 wherein d = 2, k = 10 and r = 5. 3. The method of claim 2, wherein d = 2, k = 10, and r = 8. 3. The method of claim 2 wherein d = 2, k = 11, and r = 5. The method of claim 2, wherein d = 2, k = 11, and r = 8. 3. A method according to claim 2, wherein d = 2, k = 12, and r = 5. The method of claim 2, wherein d = 2, k = 11, and r = 8. The method of claim 1, wherein the predetermined condition k is 8 or more and r is 5 or more. 10. The method of claim 9, wherein d = 1, k = 8, and r = 5. 10. The method of claim 9, wherein d = 1, k = 9, and r = 5. 10. The method of claim 9, wherein d = 1, k = 10, and r = 5. 10. The method of claim 9, wherein d = 1, k = 11, and r = 5. An apparatus for converting data words to be recorded on a recording medium into modulated data, the apparatus comprising: By adding different digital words of r bits to the input data word, a plurality of selection sequences are generated, and the generated plurality of selection sequences are generated according to a predetermined m / n coding ratio. Modulated into a sequence satisfying the condition, wherein the values of r and k are such that the low frequency suppression characteristic for the modulated (d, k) condition matching sequences is 25 dB or more and the average coding rate is 0.53 or more. Means for using, and The presence of a synchronization pattern, a string of zero consecutive strings, or a string with a long run of variation Tmin in the modulated (d, k) condition matching sequence is measured so that recording to the recording medium is performed accordingly. And means for selecting one (d, k) condition matching sequence for the sequence of data words into a modulated signal. 15. The apparatus of claim 14, wherein the predetermined condition d is 2, k is 10 or more, and r is 5 or more. 15. The method of claim 14, wherein the predetermined condition d is 1, k is 8 or more, and r is 5 or more.