JPS63233612A - Data compression circuit - Google Patents

Abstract

PURPOSE:To realize the acceleration of a data compression processing, by forming a data compression/expansion circuit in pipeline structure by introducing a compression code of byte fixed length possible to be processed easily in an information processor, and preceding a bit of status information by attached data in the compression code. CONSTITUTION:In a reference means 1, original data is referred with fixed length, and as a referred result, status information representing all white, all black, and mixed black and white, etc., are generated by a status generating means 2. The status information are compared, and it is compared whether, for example, the all white or the all black is continued by a comparison means 3. And when it is continued, the number of continuance is counted by a counter 4. Meanwhile, the status information are sent after the information are unified so that the length are set at fixed length, and next, the original data, or a bit of attached information, that is, the data in which all of the number of continuance of specific information are generated with prescribed fixed length is sent out. In such a way, it is possible to compress the data when the all white or the all black are continued.

Description

[Detailed Description of the Invention] [Summary] The present invention solves the problem of increasing the complexity of control circuits and improving processing capacity and performance by using variable length compression codes in data compression circuits in image data processing systems. In order to solve this problem, we introduced a compression code with a fixed byte length that can be easily processed by an information processing device, and in this compression code, the status information is placed before the wallet data of the status information, and the data compression and decompression are performed. By using a vibrating circuit structure, data compression processing speed can be increased.

[Industrial application field]

In recent years, in information processing systems, there has been a growing demand for multimedia information processing that handles image information in an integrated manner in addition to conventional code data.

The present invention relates to a process of converting image information into code data based on the above requirements, and relates to a data compression circuit using a fixed length compression code to speed up data processing.

[Prior art and problems to be solved by the invention] Typical conventional compression codes for image data include MH and MR codes that use run lengths. The compression ratio is set with priority given to a relatively slow processing device such as a facsimile, and there is a problem in increasing the processing speed.

In other words, even if the reference unit of the original data is increased in order to perform high-speed compression processing, it is necessary to detect change points in the reference data and calculate the run length, so the reference data must be processed serially, and the processing However, the speed could not be increased. Furthermore, since variable-length data is used, it cannot be processed by commonly used fixed-length data processing devices, and special equipment is required.

In view of the above-mentioned problems, the present invention makes the reference unit of the original data the same fixed length as the compressed code, and in the compressed code, the status information is placed before the wallet data of the status information, and the data compression/expansion circuit is The pipeline structure realizes high-speed data compression processing.

[Means for solving problems]

The data compression/decompression circuit of the present invention includes a reference means 1 for referencing original data in a fixed length as shown in FIG.
A status generating means 2 that generates status information of reference data according to the output; a comparing means 3 that compares the continuous status information generated by the status generating means 2 and outputs whether or not they are the same status information; A counter 4 for counting the number of consecutive pieces of the same switch information according to the comparing means 3, a fixed length data generating means 5 for generating fixed length data consisting of a plurality of pieces of the above status information, and the original data or the above status information outputted by the counter. The conventional problems are solved by a data compression circuit equipped with a fixed-length code generation section 6 that generates a fixed-length compressed code with a consecutive number of .

[Effect]

In the data compression circuit of the present invention, the reference means refers to the original data in a fixed length, and as a result of this reference, the status generating means generates status information indicating all white, all black, white, mixed black, etc. It occurs more.

Then, this status information is compared, and the comparing means 3 compares, for example, whether or not all white and all black are continuous.

If they are consecutive, the counter 4 counts the number of consecutive ones.

On the other hand, the status information is collected into a fixed length and sent out, and then the original data or wallet information, that is, data in which the number of consecutive pieces of specific information are all generated in a predetermined fixed length is sent out. This allows data to be compressed when all white and all seats are consecutive.

〔Example〕

An embodiment of the data compression circuit of the present invention is shown in FIG.

In FIG. 2, the input control unit 7 refers to and outputs the original data in a fixed length, for example, 1 byte i, and the status generation unit 8 generates a status indicating the state of the original data referenced by the input control unit 7. Information is created using, for example, 2 bits. For example, if the reference data is image data of binary information of white and black, this indicates whether the reference data is all white, continuous black, or a mixture of black and white.

The comparison unit 9 compares the status information generated by the status generation unit 8 with previously generated status information, and detects whether or not a state in which all the original data are the same data continues.

The counter 10 counts the number of consecutive cases in which the reference data is all white or black, for example, according to the output of the comparison unit 9,
It is output as data of a predetermined fixed length.

The multiplexer 1) selects either the fixed length original data outputted via the input control section 7 or the data outputted from the counter 10, and the information buffer 12 temporarily stores the output of the multiplexer 1). It is something.

The status assembly unit 13 uses a plurality of pieces of status information generated by the status generation unit 8 and outputs them as predetermined fixed length data. For example, it uses four sets of 2-bit status information and outputs them as 1-byte length data. It is something.

The output control unit 14 selects the output data of the status assembly unit 13 and the data stored in the information buffer 12 and outputs them to the outside.Following the output data of the status assembly unit 13, data corresponding to the output data is output. This controls the output of the information buffer 12 from the information buffer 12.

Fourth, a diagram illustrating the operation of the data compression circuit shown in FIG. 2 is shown.

In FIG. 4, it is assumed that the predetermined fixed length is 1 byte, and data is referenced in units of 1 byte. Here, the reference data is composed of binary data of white and black, and 2-bit status information is generated in the status generating section 2 shown in FIG. 2 according to the 1-byte reference data. For example, if the reference data is all white for 1 byte, 00" is
If the reference data is all black, “10” is generated, and if the reference data is all white or all black continuously over multiple bytes, the status information “1)” is output, and the comparator 9 and counter 10 output the status information “1)”. The number of consecutive pieces of the same data is counted, and 1-byte data with the most significant focus as identification data is stored in the information buffer 12 via the multiplexer 1) to indicate whether the continuous data is white or black. Further, if the reference data is a mixture of white and black, O1'' is generated as status information, and the original data, that is, the reference data, is stored in the information buffer 12 via the multiplexer 1).

As a result, the four sets of status information generated are configured as a 1-byte status byte in the status assembling unit 13, and each time a 1-byte status byte is configured, it is output to the outside via the output control unit 14,
The data corresponding to the status byte is output from the information buffer 12 and used as a compressed code.

For example, if status information of '00' and '10' indicating all white and all black appear alternately in the status byte, no data is output, and the status byte contains a mixture of black and white or all white or all black. Original data or data indicating the length of continuous bytes is added as accompanying information only when status information of 01" or "1)" indicating continuous black bytes appears.

Next, FIG. 3 shows an embodiment of the data decompression circuit.

In FIG. 3, the input control unit 20 refers to the input compressed code in a predetermined fixed length, for example, byte fixed length, and according to the reference data, if it is a status byte, it is stored in the status buffer 21 as the original data or If the data indicates the number of consecutive pieces of specific data, it is output to the original data buffer 22 and counter 23, respectively.

The status buffer 21 determines the input status information of a predetermined fixed length, controls the pattern generation unit 24 and the counter 22, and generates output data of a predetermined length that is all white or all black, and also indicates data that is a mixture of black and white. In some cases, the output controller 25 is controlled to output the data stored in the original data buffer 23. As a result, by configuring the data decompression circuit in this way and inputting the compression code, it becomes possible to output data corresponding to the original data via the output control section 25 in a predetermined fixed length, for example, in units of bytes.

FIG. 5 shows an embodiment of the present invention.

The data compression circuit 35 receives the original data via the original data bus 41 and the outgoing cover couch 30, and also receives an ACK signal indicating that the data is valid via the input buffer 3).

This ACK signal is output by the data compression circuit 35 in response to the TREQ signal indicating that data can be received.

The data compression circuit 35 compresses the data as described above, multiplexes it with the original data by the multiplexer 37, and sends it out to the compressed code bus 42 via the input/output cover couch 39.

On the other hand, the compressed code via the compressed code bus 42 and the ACK signal output in response to the TREQ signal are input to the data expansion circuit 36 via buffers, respectively. As a result, the data is decompressed and the multiplexer 33
．． It is sent to the original data bus 41 via the input/output cover sofa 30.

〔Effect of the invention〕

As explained in detail above, according to the present invention, in the data compression circuit, by setting the data processed internally to a fixed length of, for example, 1 byte, synchronization in each processing node is facilitated, and pipeline processing This makes it possible to realize a high-speed data compression circuit by making full use of the reference and data processing capabilities of the original data or compression code.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is an embodiment of the data compression circuit of the invention, Fig. 3 is an embodiment of the data decompression circuit, and Fig. 4 is the operation of the data compression circuit. The explanatory diagram, FIG. 5, shows an example of the configuration of the data compression/expansion circuit of the present invention. In the drawings, 1 is a reference means, 2 is a status generation means, 3 is a comparison means, 4 is a counter, 5 is a fixed length data generation means, and 6 is a fixed length code generation section. Agent Patent Attorney Sada Iji - Yamei/I#, Theory 2' 1st Must 1f Jlffi Cheetai Nakabari's Rebirth - AAl1 No. 3 Former Articles/Yukan's Teyuta Li Mocking Pill 14Q◆Vi乍袵郎 Blindness〕纂4℃

Claims (4)

[Claims] (1) In a system for processing image data consisting of binary information, a reference means (1) refers to the original data in a fixed length, and a status generator generates status information of the reference data according to the reference means (1). and a comparing means (3) for sequentially comparing the status information generated by the status generating means (2) and outputting whether or not the status information is the same; a counter (4) that counts the number of consecutive pieces of status information; a fixed-length data generation means (5) that generates fixed-length data consisting of a plurality of pieces of the above-mentioned status information; and a fixed-length data generation means (5) that generates the original data or output from the above-mentioned counter (4). Fixed-length code generation means (
6) A data compression/expansion circuit comprising: (2) The data compression circuit according to claim 1, wherein the status information indicates whether the fixed length reference data is continuous or mixed specific information among binary information. (3) The above compressed code includes fixed-length data consisting of multiple pieces of status information, and the number of consecutive fixed-length pieces of data corresponding to the status information, if it indicates a sequence of specific information among the binary information. , and fixed length data representing original data in the case of a mixture of binary information. (4) The counter (4) counts the status information indicating consecutive specific information outputted from the comparing means (3), and if the number of consecutive specific information is less than the number of statuses constituting the fixed length status information 2. The data compression circuit according to claim 1, wherein a fixed-length compression code is generated by continuously displaying the same status.