JPS59225653A - Information converting system - Google Patents

Abstract

PURPOSE:To reduce a DC component and a low frequency component and also to decrease the bit error rate by corresponding an n-bit of information to be converted one to one to a selected combination and inverting the head bit every time the 2nd combination appears. CONSTITUTION:The information applied to an input terminal 1 is transferred in a shift register 2 by 8-bit each with a pulse supplied to a clock terminal 5 in the data bit rate and the information in 8-bit (B1-B8) is supplied to a converting logic 3. The said one to one conversion is attained in this conversion logic 3 and the converted information in 10-bit (P1-P10) is supplied to a shift register 4. Outputs Q1-Q3 are supplied to latch circuits b1-b3 and the latch outputs Q1'-Q3' are supplied to the conversion logic 3. Further, the timing of the pulse supplied to the clock terminal 5 in the data bit rate is detected by a detecting circuit 7 and this timing signal is suplied to a latch terminal of the latch circuits b1-b3 and a load terminal LD of the shift register 4 by each 8-bit.

Description

[Detailed Description of the Invention] Industrial Application Field This invention is suitable for use in information conversion systems, particularly when converting digital signals into signals suitable for the recording or transmission system when recording or transmitting them. Concerning information conversion methods.

Background technology and its problems For example, in a device that converts audio signals into PCM and performs magnetic recording using a rotating head without forming a guard band, problems arise due to differential output characteristics of magnetic recording and low-frequency crosstalk from adjacent tracks. In addition, low 19h:y-'=KZF
). Near 78. 6°7, □.

There is a problem with faithful reproduction of low frequencies.

Therefore, in such a device that has a narrow recording/reproducing frequency band and is required to have few low-frequency components, it is necessary to modulate the recording signal using a modulation method that has few frequency spectrum components in the low-frequency component or DC component region. .

is effective, the modulation force called NRZI
,,.

Equation is one example. This is done so that "1#" in the data signal inverts the signal, and "@0" does not invert the signal.

It is something that

However, in this NRZI modulation system, when "0#" continues, the modulation signal is no longer inverted during that time, the frequency decreases, and there is a disadvantage that the DC component and low-frequency component increase.

Therefore, information by PCM is decomposed into an arbitrary number of bits and each of them is converted into a larger number of bits to prevent a large number of consecutive 0''s.

Furthermore, when trying to perform the above-mentioned recording using a small device such as a portable device, it is difficult to make the rotary head smaller, the recording track becomes narrower, etc., and the reproduction output of 87N is poor, and the recording bandwidth is still low. There are problems such as the space being narrow.

Here, for example, with respect to S/N, it is desirable that the ratio between the detection window width (Tw) during demodulation and the minimum inversion width (Tm1n) be as small as, for example, twice or less.

Therefore, for example, a conversion method called -xi code has been proposed.

However, decoding converts 2 bits (Bl * 82) information into 3 bits ("i, P2 e P:l), and the conversion formula is Pl: P3p + B1 + B2°BtfP2 = P3p
-B1+B2 P3 = p3p+ Bl + B2 However, the suffix p is the previously converted information, f is the next converted information, and the demodulation formula is: B1 Cod Agency・P□p+P3p,Pt,"aB2;
It is given by Pz-P.

When this moth is an accordion, TW=0.67'I'
.

Tm1n = 0.67T XTmax (maximum inversion width) = 1.33T (where T is the time or wavelength equivalent to 1 bit of modulated data), where the ratio of short to Tm1n is 1.

Furthermore, a conversion method called 415 conversion has also been proposed.

415 conversion method is 4 hit 7 (F31.B2.8318
4) information in 5 bits (P1 * P2. r Pa +
P4·Ps), where the number of consecutive '0's is 2 or less in NRZI representation.

In other words, in a combination of 5 pits, 0 at the beginning or end
” are not consecutive, and the number of consecutive “O”s between them is 2.
There are 17 copies of the following. Then, the 16 sequences of 4 bits of modulated data (oooo) to (1111) are converted into the above-mentioned 17-1! It is converted in one-to-one correspondence with any 16 letters among the i letters.

In this way, it is possible to perform conversion such that the number of '0#'s between 1'' is always 2 or less.

In this 415 conversion method, sugar = 0-8 T%Tm
1n = 0.8 T, 'I'max = 2.4
T, where the ratio of TW to Tm1n is 1.

However, in these methods, a DC component exists in the signal after NRZI conversion.

If there is a DC component in the signal after the training, that is, the recorded signal, for example, for the original signal shown in Figure 1, the part that should originally be reproduced as shown in Figure 1B is In reality, as shown in Figure 1C, the direct sales component is offset and reproduced to 0, and the output signal becomes a signal whose time axis has been varied as shown in Figure 1.
Unable to reproduce faithful digital waveforms.

For this reason, frequencies etc. are determined taking these into consideration, so
There were problems such as the inability to increase the recording density.

On the other hand, for example, 16/20 conversion, 24/ao conversion, etc. can perform conversion without a DC component.

However, in these methods, the constraint bit length required for both conversion and inverse conversion is extremely long, the device becomes extremely large, and error propagation is large, making it impractical.

Further, Tmin and 'I'max correspond to the lower limit and upper limit of the frequency of the recording signal, respectively, and if these ratios are too large, problems will arise in terms of frequency characteristics and the like. Therefore, this ratio is 3
It needs to be less than double.

Purpose of the Invention In view of the above, the present invention proposes an information conversion method that can reduce DC components and low frequency components and has a short constraint bit length.

SUMMARY OF THE INVENTION This invention converts m bits of information into n bits of information larger than m.
In the signal after ZI modulation, the number of successive bits at the same level is 3 or less, and the first combination is such that the accumulation of DC in the n bits is 0, and the accumulation of DC is controlled to be 2 or less. A possible second combination and a third combination in which the DC accumulation is fixed to 2 or less, and the m-bit information is one-to-one with the combination selected under the above conditions.
At the same time, when the second combination is used, the sign of the DC accumulation is stored, and when the second combination is used next, the DC accumulation is stored as the storage. is an information conversion method in which the first bit of the second combination of the above methods is converted so that it has the opposite sign, and the bit error rate is improved by reducing DC components and low frequency components, High-density recording becomes possible.

Embodiment Hereinafter, an embodiment of the present invention will be explained, taking as an example a case where 8-bit information is converted to 10-bit information, and FIGS.
This will be explained in detail based on FIG. 9.

Here, 8 bits (B1 r B2 + B3 + B
4, B5 *B6IB71B8) information in 10 bits (Pl, B2°B3・B4.B5・B6.Pl
・B8・B9・Plo), so 8
There are 28 forms in which information on bit (B1-Be) can be obtained.
= 256 letters.

On the other hand, regarding (Pi to P10), in order to remove the DC component, the signal after NRZI modulation must be
It is sufficient that 5 bits among the bits be positive (1) and 5 bits be negative (0). Note that in order to set Tmax/Tm1n = 3, the condition is that the number of consecutive 'O#'s in the NRZI expression is 2 or less, that is, the number of consecutive same level pits in the modulated signal is 3 or less.

After considering these conditions, further using NRZI expression,
The number of first or last 0# is classified as 0, 1, or 2, and the combinations for each case are shown in Table 1. The number of consecutive 0's in a part can be set to 2 or less, for example, when the number of first 0's is 1 or less and the number of 0's at the end is 1 or less.However, in this case, In this case, the number of combinations is 59 + 28 +
There are only 37 + 17 = 141 letters. This is less than the number of 8-bit 256 combinations, and with other selection methods, the number would be even smaller.

Therefore, combinations other than the DC component O will be considered. That is, for example, when the number of the last 'O' is one or less, the number of combinations based on the number of the first 'O#' and the amount of accumulated DC is as shown in Table 2 below.

Table 2 Here, regarding the accumulated amount of DC, for example, as shown in FIG. 2, the case where the last of the previous combinations ended as negative (0). Therefore, if the previous combination ends with a positive (1), the positive and negative signs are reversed. : Also, for example, for a combination where the first bit is "0", if this first bit is converted to "1#", the sign of DC accumulation will be reversed as shown in Figure 3, and for example, as shown in Table 2. By using the combinations where the DC accumulation is +2.-2 and the first bit is 0'', 28 + 34 = 62 combinations, the above-mentioned 141 combinations without DC component and this first combination are combined. 62 combinations of 2 and the remainder of this second combination, that is, the accumulated amount is +
2. 53 third combinations fixed at −2, totaling 25
The six combinations are made to correspond one-to-one with the 256 combinations of 8 bits. Each time the second combination appears, the first bit is converted so that the DC accumulation is alternately positive and negative.

In other words, as shown in Figure 4, when the second combination appears, count the number of inversions p (the number of "1's") from the second bit, and calculate the number of times p (number of "1's") until the next second combination appears. ,
If the number of inversions is an even number, the first bit (
Convert the arrow) to @1#, and if it is an odd number, leave it as "θ''' as shown in FIG. 4B.

As a result, even if controllable combinations continue to DC=0 or DC-+2, or combinations are fixed at D, C=+2 or -2, the next controllable combination will be DC=±2. As a result, these factors cancel each other out, and the DC component becomes 0 in the long run no matter how the combination continues.

Note that the accumulation of DC is +2. The third combination fixed at −2 requires three copies υ as described above, but in reality, Table 3
As shown in Table 3, if 62 pieces are used as the second combination, only 4 + 46 = 52 υ combinations remain as the third combination. This means that the second combination differs from ``tlm'' in that only the first bit is 10.
This is because the two codes after the 2nd bit are considered to be one code, so twice as many codes as other combinations are used. There are 34 types of DC=-2 with the first bit of 11", but 28 of them have the first bit of 601# and are used by inverting the first bit of DC=C2O4 to '1#. Therefore, there are no 6 letters, and there are 80 letters for DC=+2,
This is because 34 of them are used as the first bit inverted in the second combination, so there are only 46 copies.

Therefore, as the second combination, 61 of the 62 letters are used, and the first 2 bits of the remaining 1 letter are set to 01...
``...'' and '11...'' are used as two passes of the third combination in which the DC accumulation is fixed at +2 and -2, respectively. 1 combination of
Try to increase it by one.

The following Table 4 shows the 256 letters selected in this way.
4 In this Table 4, those indicated by ■ are car 2. which is originally the second combination. This is the third combination. Of the second combination divided into these two, the first Pito was '11...
”, DC=-2, first 2 bits are 1 inch...
・'', the combination of 3 for each of DC=-2 is obtained, but the opposite is also true.

An example of 256 codes created using this method is shown in Table 5 below.

In Table 5, the code corresponding to data 8D and BC is the second combination divided into two and used as the third combination. Note that the arrangement of each combination in Table 5 does not take into account the probability of occurrence of day and evening. Generally, in the case of PCM data, all bits are "0#"
When , it represents no signal, and the probability of its occurrence is high, but the data that appears when the amplitude swings over the full dynamic range rarely occurs. Therefore, it is preferable for an actual system to create a conversion table that takes into account the difference in the probability of occurrence of such data.

FIG. 5 is an example of a device that performs conversion according to the above-described method. In the figure, (1) is an input terminal, (2) is an 8-pit shift register for input, (3) is conversion logic, and (4 is
) is a 10-pit shift register for output.

The information supplied to the input terminal (1) is then υ by the pulses applied to the clock terminal (5) at the data bit rate.
8 bits are transferred through the shift register (2), 8 bits at a time.
The bit (B1-Bs) information is fed to the conversion logic (3). With this conversion logic (3), the above one-to-one
The conversion is performed and the converted 10 pitsu) (P1 to PI
The information of O) is supplied to the shift register 7, evening (4).

Furthermore, the number of inversions of the signal after conversion is detected. Here, since the number of inversions is known in advance for each combination, for example, information on the number of inversions (only whether the number of inversions is an odd number or an even number is required; for example, if it is an odd number, " 1”) can be output simultaneously. These outputs Ql to Q3 are the latch circuit (6
1) to (63), and the latch outputs Ql' to Q
3' is fed to the conversion logic (3). Furthermore, the timing of the pulses supplied to the clock terminal (5) at the data bit rate is detected by the detection circuit (power), and this timing signal is sent to the load terminal LD of the shift register (4) and the latch circuit (61) every 8 data pits. ~(63) are supplied to the latch terminals.

When converted to the first combination described above, the output 10 bits are output as they are to the shift register (4), and the number of inversions P of the output first combination is
and inputs Ql' to Q from latch circuits (61) to (63)
3', output '4-Qa is taken out as DC accumulation information as shown in Table 6 below. However, when the DC accumulation is zero (DC=0), if the number of inversions P is an even number (0''), the input Q1' from the latch circuits (61) to (63)
~Q3' values are taken out as the IT outputs Ql~Q3 and latched into latch circuits (61)~(63), respectively.
Transmitted to the next combination. Moreover, at this time, if the number of inversions P is an odd number (1″), the latch circuits (61) to (6
The values of the inputs Ql' to Q3' from 3) are reversed in polarity, taken out as outputs Ql-Q3, and latched by latch circuits (61) to (63), respectively, to form the next combination. transmitted to.

Table 6 When converting to the second combination, as shown in Table 7 below, the sign of the accumulated DC in the current combination and the values from the latch circuits (61) to (63) are determined. Depending on the inputs Q1' to Qa, the first bit (N(1)) is converted to 'B' or '0#, and the converted first bit (N(1)) is changed to the number of inversions P after the second bit, etc. Based on this, output Ql-Q3 is taken out as information on the accumulation of DC.

In other words, in Table 7, 10 indicates the first pix of the current combination) When N(1) is "0#", the DC accumulation is +2. -0 indicates the first pix of the current combination) N(1) is "0"'', the DC accumulation represents -2.If the values of the inputs Ql' to Qa' from the latch circuits (61) to (63) are 1 in the case of 10, then the previous Since the combination has a DC accumulation amount of at least 1 or more, it is preferable to control the DC accumulation of the current combination in the negative direction, so the first bit is inverted and set to 11#.Therefore, At this time, the shift register (4) is supplied with information in which only the first bit of this current combination is inverted to 11#.

Then, by inverting this first bit, the current accumulation of the current combination becomes -2, so this and the latch circuit (61
) to (63) are added.

Whether or not this added value is used as it is as output Q1 to Q3 depends on the number of inversions P after the second bit of the current combination and the first bit.
) is determined by the equality of the results.

That is, when the mod 2 result is an even number 'O#, the above-mentioned added value is output as is as information on the accumulation of 1 DC current, and when it is an odd number "1#", its polarity is inverted and output.

For example, if we consider the case where the DC accumulation information is 1 bit, that is, Q1', and the first bit is inverted to @1'', the DC accumulation of the current combination is +2 + C2.
When this is added to the value 1 of the input Q and / from the latch circuit (61), it becomes -1. Therefore, if the number of inversions after the 2nd bit at this time P "0" and the first bit "'1# are mod 2, it becomes @1#, so the above addition value -1 is set to 1.
The latch circuit (61) K outputs this as the output Q1.
Latch and transmit to next combination.

In addition, the input Q1' from the latch circuits (61) to (63)
~ If the value of Q3' is -1, the amount of DC accumulation in the previous combination is at least 11 or less; there is no need to particularly control the accumulation of DC in the current combination; The bit can be up to '0' without being inverted.

Then, as mentioned above, the accumulation of DC at this time, ie +
2 and input Q1' from latch circuits (61) to (63)
The value of Q3' is added, and this added value is used as outputs Q1 to Q3 to be transmitted as DC accumulation information depending on whether the result of mod 2 of N(1) is even or odd and the number of inversions P and the leading pip. For example, if we consider the case where the DC accumulation information is 1 bit, the first bit is not inverted, so the current combination of DC accumulation remains +2, and this and the input from the latch circuit (61) When the value of Q1/-1 is multiplied by force n, it becomes 1. Therefore, if we mod 2 the number of inversions P″″0# after the second bit and the first bit “′0″ at this time, it becomes @0″, so the latch circuit (
61) and transmit it to the next combination.

On the other hand, in the case of -C, the same can be considered; if the values of the inputs Ql' to Qa' from the latch circuits (61) to (63) are 1, the previous combination is at least 1 or more. Therefore, there is no need to particularly control the accumulation of DC in the current combination, so the first bit may remain @0# without being inverted. Then, add the DC accumulation at this time, that is -2, and the values of inputs Q1' to Qa' from the latch circuits (61) to (63), and calculate this force 0 value as the number of inversions P and the first pitch) N( Depending on whether the mod 2 result of z) is even or odd, the outputs Q1 to Q3 are transmitted as DC accumulation information. For example, if we consider the case where the DC accumulation information is 1 bit here, the first bit is not inverted, so the DC accumulation of the current combination is also -2, and from this and the latch circuit (61). Adding the value 1 of the input Q1' of is -1
becomes. Therefore, the number of reversals P after the second bit at this time is
When @0# and the first bit “0” are mod 2, it becomes “0”
Therefore, the added value -1 is latched as is as the output Ql in the latch circuit (61), and transmitted to the next combination.

Inputs Ql' to Q3 from latch circuits (61) to (63)
If the value of The first bit is inverted to "1". Therefore, at this time, information in which only the first bit of this current combination is inverted to "1" is supplied to the shift register (4). Then, by inverting this leading bit, the current combination of dragon accumulation becomes +2, so this is added to the values of inputs Ql' to Qa' from the latch circuits (61) to (63). This added value is calculated as the number of inversions P after the second bit of the current combination and the first bit) N(1) mod
Depending on whether the result of step 2 is even or odd, it is transmitted as outputs Q1 to Q3, which are DC accumulation information, as described above. For example, if we consider the case where the DC accumulation information is 1 bit, that is, Q1', and if we invert the first bit and make it @1'', the DC accumulation of the current combination will be -2 and +2. If you add this and the value -1 of the input Qi' from the latch circuit (61), it becomes l. Therefore, the number of inversions after the 2nd bit at this time P@0# and the first bit ""1" are mod 2 then 1#
Therefore, the above added value 1 is inverted to -1, this is latched by the latch circuit (61) as the output Q1, and is transmitted to the next combination.

In this way, the second combination receives information on the DC accumulation up to the previous combination and functions to control its leading bit so that the DC accumulation approaches zero.

Also, when converted to the third combination, 10 of the output
Bituto is one of them! At the same time, the third output
The number of inversions P and latch circuits (61) to (63) of the combinations of
), outputs Ql-Qa are taken out as shown in Table 8 below in response to inputs Q1/-Q3'.

That is, in Table 8, the accumulation of DC is +2 (DC=+
In case 2), if the number of inversions P is an even number (“O”), the input Q1/~Qa' from the latch circuits (61) to (63)
If the number of reversals P is an odd number (
'1#), add +2 to the values of inputs Q1' to Q3' from latch circuits (61) to (63) and reverse the polarity, and take out the values as outputs Q1 to Q3, respectively. The signals are latched in respective latch circuits (61) to (63) and transmitted to the next combination as DC accumulation information. On the other hand, when the DC accumulation is -2 (DC=-2), if the number of inversions P is an even number, the input Q1 from the latch circuits (61) to (63)
'~Qa' plus -2, and the number of reversals P
If is an odd number, -2 is added to the values of the inputs Q1' to Qa' from the latch circuits (61) to (63), the polarity of which is reversed, and the value is taken out as the outputs Q1 to Q3. It is latched into the husband latch circuits (61) to (63) and transmitted to the next combination as DC accumulation information.

However, what should be noted here is that the accumulation of DC is +2 or -
This is the case when a third combination of 2 appears in succession, resulting in a continued increase in the accumulation of direct current. Therefore, when selecting each combination, the third
It is preferable to select as few combinations as possible. Furthermore, the probability of occurrence of the modulated signal may be reduced by converting a modulated signal with a low probability of occurrence into the third combination. In other words, in general, as shown in Figure 6, music signals, etc., rarely have a level that reaches the maximum value of 10P1 and the minimum value -P, and are mostly distributed below the mid-range level shown by diagonal lines in the figure. , the first combination of DC=O is placed in this part, and the second combination that can be controlled to DC=±2 is placed, and DC-+ is placed near the peak value.
In other words, a third combination fixed to 2 is arranged.

In this method, if N bits of DC storage information bits are used, 2N DC storage states can be transmitted, so the amount of DC storage is -ω, ... -5, -3, -1 .

+1. +3. It can take any value with two steps of +5..., +ω, and therefore the information on the accumulation of DC becomes extremely large. Therefore, here, the signal that transmits the DC accumulation information is limited to a few bits (in the case of 3 bits in Table 8). For example, as shown in Fig. 7, if the DC accumulation information is 1 bit, the DC The accumulated amount of is -1, +1
For binary values, 2 bits, -3, -, 1, +1, +
4 values of 3, -7, -5, -3, -1 for 3 bits,
Information on eight values of +1, +3, +5, and +7 is transmitted, and any value exceeding these is transmitted as the respective maximum or minimum value. In other words, 9. For example, if the information on DC accumulation is 2 bits, the amount of DC accumulation is +3. Even if there is a value exceeding -3, the maximum value is transmitted as +3 and the minimum value as -3.

Incidentally, in Table 8, the maximum and minimum values mentioned above are 1 and -1 when the DC accumulation information is 1 bit, and 3 when it is 2 bits.
and -3,3 bits are limited to 7 and -7. Therefore, for example, in Fig. 7, the information on the accumulation of DC is 1
In the case of bit, there is currently +1 DC accumulation, then D
When a combination fixed at C=+2 comes, the accumulated amount of DC will be +3, but when the information bit is 1 bit, it will be +3.
Since only the state of DC accumulation of 1 can be transmitted, +1 is transmitted as the DC accumulation amount for the next combination.

Figure 8 shows the relationship between DC accumulation information and DC component reduction in this method, with particular emphasis on the low range of the frequency spectrum. 00, curves C and C are the cases where the information bits are 1 bit and 2 bits, respectively. Than this,
It can be seen that the direct current component is reduced by transmitting information about the accumulation of direct current.

Returning again to FIG. 5, the contents converted to 10 bits and written into the shift register (4) as described above are 5/4 times the clock of the input signal supplied from the clock terminal (8). The signals are read out sequentially according to the clock signal of the frequency.This read signal is sent to the JK frig float circuit (9).
According to the clock signal from the terminal (8) which is applied to the clock terminal of the free-lag flop circuit (9), the NRZI-modulated signal is output from the free-lag flop circuit (9) to the output terminal ( II.

FIG. 9 shows an example of a device for demodulation, and in the same figure, the signal from the input terminal αB is N1(,Z
10-bit shift register 0 through demodulation circuit a of I
3) and is transferred through the shift register (10) in units of 10 bits by pulses at the code bit rate from the clock terminal 04). Then, the information (Pi to PIO) from this shift register is supplied to the conversion logic (one).Then, demodulation is performed by the above-mentioned one-to-one inverse conversion, and the demodulated information (81 to 13s) is supplied to the shift register (16), and the clock terminal (14)
The timing signal (pulse for each block) detected by the timing circuit αn is transferred to the shift register lle.
Each time the voltage is applied to the load terminal LD of The contents of the shift register (16) are then transferred to the clock terminal (18).
) is shifted by a pulse applied at the data bit rate to the output terminal (11). When 10 bits from the second combination described above are supplied, the first bit is ignored and the inverse conversion is performed. be made to be done.

Conversion and demodulation can be performed in this way.

In this method, Tw=Tm1n=0.
8T.

Tmax) (= 2.4 T. Therefore, the above-mentioned Ga Accord has the disadvantage of an increase in low-frequency components due to the widening of Tmax, but with this method there is no DC component. This advantage offsets this disadvantage and allows for better recording and reproduction.

In addition, when compared with the above-mentioned 415 conversion method, the recording density is the same, and since there is no DC component in this method, there is no time axis fluctuation of the reproduction signal mentioned above, and recording and reproduction at a higher frequency is possible. In addition, the recording density can be increased.

However, the constraint bit length does not become long as in the above-mentioned 16/20 conversion and 24/30 conversion.

Note that the above embodiment deals with converting 8-bit information into 10-bit information, but the same applies to other cases where m-bit information is converted into n-bit information, which is larger than m. This can be applied, for example, when converting 6-bit information to 10-bit information (T, v = Tm1rl =
0.6 T, Tm2) (= 1.2 T), it may be performed as follows.

That is, since Tmax /Tmin = 2,
In the NRZI expression, the number of consecutive "θ" is up to one, and the combination is such that there is always @1# on both sides of the thumbnail 0".

In addition, in order to prevent a series of "O#s" from occurring between each combination, that is, the connection between each 10-bit pattern, t-
The number of ``10'' at the beginning of the combination is 1 or less, so that the number of ``b-o'' is one or less, that is, ``old...''
or 1...'', the number of @0# at the rear end is limited to 0, that is, 1...1'.

The number of 10-bit combinations that satisfy these conditions is
The result is as shown in Table 9 below.

Table 9 According to this Table 9, the first combination 50 (29+21) with no DC component (DC=0) and the DC accumulation +2
．． -2 and the first bit is '0', the second combination 13 (9
+4) 63 combinations are possible. Then, the remaining DC accumulation is +2 and the first bit is 10...
``...'', and there are no combinations with DC accumulation of -2 left, so a pair of combinations that can control DC accumulation, that is, a second combination, cannot be created. Select the remaining 1 case from the 12 cases where the DC accumulation is +2 mentioned above, and use this as the third combination.
Make one-to-one correspondence with the combination of four letters.

This allows you to configure a combination for converting 6-bit information into 10-bit information, and then all you have to do is arrange a shift register corresponding to the number of bits and perform signal processing in the same manner as described above using conversion logic, etc. good.

Effects of the Invention As described above, according to the present invention, in the signal after NRZI modulation, the number of successive bits of the same level is 3 or less, and the accumulation of DC in n pits of conversion information becomes O. 1, a second combination in which the DC accumulation can be controlled to 2 or less, and a third combination in which the DC accumulation is fixed to 2 or less, and the m bits of the information to be converted are set under the above conditions. By making a one-to-one correspondence with the combination selected in It is said that the error rate is improved and high-density recording is possible, and the constraint bits can also be shortened. In particular, a modulation method with a large field, Tmax/Tm1n of 3 or less, and few low-frequency components is suitable. It is useful for use in rotary head type recording devices, etc.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the conventional method, Figure 2~
FIG. 4 is a diagram for explaining this invention, FIG. 5 is a configuration diagram showing an example of a conversion device used in this invention, and FIG.
Figures 9 to 8 are diagrams for explaining this invention;
The figure is a configuration diagram showing an example of a post-adjustment device used in the present invention. (1) is an input terminal, (2) and (4) are shift renostars, (3) is a conversion logic, (5) I (8) is a clock terminal, (61) to (6a) are latch circuits, (7)
is a timing circuit, (9) is a Flinofron circuit, (
Io) is an output terminal. - Power Figure 5 Figure 6 Section I m Number of stages (KHz) Figure 7 Figure n Claims In converting m-bit information to n-bit information larger than m, the above n-bit information is The information is processed so that the number of consecutive bits at the same level is below a predetermined number of bits in the signal after NRZI modulation, and the accumulation of DC in the n bits is 0.
A second combination in which the DC accumulation can be controlled to 2 or less, and a third combination in which the DC accumulation is fixed to 2 or less, and the m-bit information is is in one-to-l correspondence with the combination selected under the above conditions, and when the second combination is used, the positive or negative sign of the DC accumulation is stored, and then the second combination is stored.
An information conversion method that converts the leading bit of the next second combination so that when the combination is used, the accumulation of the DC has a sign opposite to that stored.

Claims (1)

[Claims] In order to convert m bits of information into n bits of information, which is larger than m, the above n bits of information should be set so that the number of successive bits of the same level is 3 or less in the signal after NRZI modulation. , a first combination in which the DC accumulation in the n bits is 0; a second combination in which the DC accumulation can be controlled to 2 or less; and a second combination in which the DC accumulation is 2 or less.
A third combination is fixed as below, and the m-bit information is in one-to-one correspondence with the combination selected under the above conditions, and when the second combination is used, the DC The positive/negative sign of the accumulation is stored, and the leading bit of the next second combination is stored so that when the second combination is used next, the DC accumulation has the opposite sign to that stored. An information conversion method that converts information.