JPS58147266A - Digital modulating method - Google Patents

Abstract

PURPOSE:To prevent the generation of waveform strain by performing binary code transmission which uses a magnetic recording and reproducing device, etc., as a medium in such a digital modulating method that the difference between the maximum and minimum of inversion intervals is small. CONSTITUTION:Input data from a terminal 2 is led out of a shift register 1 in the order of Y, Z, A, B, C, and D and supplied to a combinational circuit 4. Input data A', on the other hand, is inputted to terminals J and K of an FF3, outputs of Q and inversion Q' are supplied to the circuit 4. Then, one bit of data A from the circuit 4 is converted into two bits P1 and P2. The output of the circuit 4 is supplied to FFs 5 and 6 and a selector 7 and at outputs of the FFs 5 and 6, modulation outputs (a) and (b) before corresponding to the bit Z of the input data appear and are supplied to the circuit 4. The selector 7 outputs the bits P1 and P2 in order at a transmission rate by a half rate of the input data to obtain modulated data at an output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital modulation method that is applied when transmitting a co-valued code using a magnetic recorder and reproducing device, such as a two-rotation disk, as a medium.

In this invention, the minimum interval Twin of two inversion (transition) functions is T (T is the time per bit of input data), the maximum interval Tmax is λ, 5T,
The unit TV of the inversion interval of the modulated wave is 0. ! This is a digital modulation method with f T and no DC component spectrum.

Conventionally, (Tm1n==T + Tw=0-3 T
) is the MFMFM method (Tmax = 2T) as a digital modulation method. ! ;T)'s M
” FM methods are known, but these have a spectrum of DC components.

Since this invention does not have a spectrum of DC components, even when a rotary transformer is involved and it is difficult to transmit DC and low-frequency components, such as in a rotating head type recording/playing device, the waveform can be This can prevent distortion from occurring. Further, in the present invention, since the ratio (Tm□!1) between the Tmax minimum inversion interval and the maximum inversion interval is small, the frequency spectrum 2m of the modulation waveform is concentrated in a narrow range. Therefore, even if the bandwidth of the Anzo or reproducing amplifier is narrow, it is easy to design one circuit).
It can also reduce noise and improve the error rate of reproduced waveforms.
Can be made smaller. Along with this, P for self-clock extraction
The design of the LL circuit can be facilitated.

An embodiment of the present invention will be described below.

In this example, the cobit or O of the bits of the first value CO)
The first group consists of consecutive bits of first value (1) sandwiched by bits of .

11th! The first group, which is modulated according to the modulation rule shown by IK, and which consists of a block of only / bits that do not contain O, is modulated according to the modulation rule shown in FIG.

0 always has a block boundary before or after it, and θ with a boundary before and θ with a boundary after appear alternately. Therefore, if the last appearing 90 is θ with a boundary before it, the next / will be modulated (according to the rules shown in Figure 1),
If the rear boundary is O, it is modulated according to the rules shown in FIG.

In the first all, N indicates the number of l's interposed between one O's function of the input data.

When CM=0), in the case of the input data oot-;, 0 and / are inverted at the bit cell delimiter,
This is the inversion interval of T.

When (N=/), the input data is inverted at the center of l bit cells. Therefore, 1 reversal interval is /,! F T
, /,! f”r:.

When (N=Y), convert to 00////θ0.

(N=3) When O, perform 000/100100tlC conversion.

When (N≧t) and (N=con), the first 0 is set to a low level, and after that, high and low levels are alternately repeated for each λ pit of the input data.

If (N≧5) and (N=,2n+/), the first θ
is a low level, λ and sT are repeated twice, and the remaining period is set to koT.

It should be noted that there may be a waveform with a % value as shown by the broken line, with 0 or / before or after the clock shown in FIG.

First, the first group causes an inversion at the center position of the bit cell of the original input data. Therefore, no matter how many l's are consecutive, one inversion interval is T.

According to the modulation rules shown in FIGS. 1 and 2 above, the sum of the low-level periods and the sum of the high-level periods in the /Zoroku are equal, and a series of data consisting of multiple Zoroku A similar relationship holds true for the DC component, and it can be made to have a dangerous DC component spectrum.

FIG. 3 shows the configuration of a modulation circuit according to an embodiment of the present invention, in which input data is supplied from an input terminal 2 as a serial input of a shift register indicated by 1. The input data is (
Y→2→A→B→C→D) OJ[The inverted value of each bit is taken out from the 4 shift register 1 and supplied to the combinational circuit 4. Also, input data τ is I
The outputs Q and Q of this flip-flop 3 are supplied to a combinational circuit 4. If the output Q#ib of this flip-flop 3 appears at the end up to z and 90 gives the boundary of Zoroku before it, 0. If a boundary is given after that, it becomes l. Then, the /bit of input data A from the combinational circuit 4 is PI and P
, converted to Kobit.

The output of this combinational circuit 4 is the D-type fritz 5, 6.
and is supplied to the selector 7. This flip-flop 5
．． 6, the previous modulation outputs a and b corresponding to bit Z of the input data appear.

This is supplied to the combinational circuit 4. Further, the selector 7 sequentially outputs simultaneously occurring λ bits P+ and P+ at a transmission rate of i of the input data, and modulated data is obtained at the output terminal 8. This modulation data is (a-
1) The order is b-+Pl→Px).

The combinational circuit 4 generates output pins Pl and Pl according to the following logical equations.

pl=b°-(A+Q-B-('Σ-10a),-(
=,c +D))P,=A-(:Q+Z-(100+C
-″D) + Z-a eyelid (B・C-D1b・(100Ma・i)
)] According to the above modulation circuit, (0/l//100...
...) For 0 input data, a modulated output as shown in Fig. S is generated. In Figure S, the one shown in the upper row is defined as the one that appears first and has a boundary (indicated by .) in front of it (Q=0).

Next, five successive /s are modulated according to the rules shown in Figure 1, which is a good technique. In addition, in Figure S, the one shown in the lower row is defined as the one that appears first and has a boundary after that (90).
Q=/), followed by /, is a waveform modulated according to the rules shown in FIG.

Figure 3 shows the configuration of the demodulation circuit Q, in which a modulation signal is input from the input terminal 10 (a→b→C
→d→e), and is supplied directly.

τ, c, d, and e are supplied to the combinational circuit 11.

Bit A corresponding to b and C of the modulated signal is connected to combinational circuit 1.
Output from 1. Also, the period O when the modulation signal is C and S Te.
Then, a detection signal that becomes O is generated from the NAND gate 12 when the next period 1 begins.

The output of this NAND date 12 determines that the cobit division of the modulated signal is correct. This WANDr
- The output of the gate 12 is input to the JK Fritzofrodde 13. This J input is always /.

A clock input from terminal 14 is provided, typically.

Nine clock pulses appear from the flip-flop 13, which are divided by i, and are supplied to the D-type Rizzo-flop 15 as the p-clock input. and.

When the output of NAND f-) 12 becomes O, the output of flip-flop 13 becomes /, and phase matching is achieved. The output of the combinational circuit 11 is supplied as a data input to this flip-flop 15, and demodulated data is taken out to an output terminal 16.

Note that the phase alignment of the modulated signal is performed using a synchronization signal (
This may be done by inserting a bit pattern (which does not normally appear) and detecting this synchronization signal.

Combinational circuit 11 generates a demodulated output according to the following logical formula.

A=alIb+c+dlIe In addition, the combinational circuit 4. of variable 11 circuits. The combinational circuit 11 of the W4 circuit can be realized by a ROM.

As can be understood from the description of the above-mentioned embodiment, according to the present invention, the modulation signal does not have a DC component spectrum and is
Digital modulation with a small difference between the maximum value and the minimum value of the inversion interval can be performed. Therefore, if DC components and low frequency components cannot be transmitted, 4. It can also prevent waveform distortion.

The frequency spectrum of the modulated waveform is concentrated in a narrow range, further facilitating self-clocking.

FIG. 1114 shows the modulation rule of another embodiment of the present invention, which is applied to a first group of consecutive blocks of / bits sandwiched by 00 pits. The second group of blocks containing only / bits that do not contain 0 is modulated according to the modulation rules shown in FIG. 2, as in the previous embodiment.

#17 Compared to the modulation rule shown in Figure 17, there are differences between the case (N=, ?) and the case (N22) and (N=2n+/). t), (N=3), it is modulated as (T→ko, 5T-4/, 5T), and (N≧3), (N=
In the case of Jn+/), the end is (ko,,l-T→/,!
;T), and the others are separated by UT.

As shown in FIG. 7, three consecutive bits Z of the input data
, A, B, and the modulated signal a corresponding to 2.

A modulation signal Pl+P corresponding to the input data is generated from the fifth-order logical expression.

pi = τ・(X+η・B・(τ+&))P,=A・(
Q+100・(Z+a)) Therefore, when the input data similar to that in Fig. S is modulated,
As shown in FIG. 5, two sets of modulated signals can be obtained depending on whether the block boundary is before or after the first O0 that appears. Further, the demodulation rules are the same as those described above, and the demodulation rules for other embodiments described below are as follows.
are considered to be the same.

When the modulation rules shown in FIG. 6 are used, the number of input data bits required during modulation can be reduced, and the configuration of the modulation circuit can be made simpler.

FIG. 9 shows modulation rules in another embodiment of the invention. For the first group consisting of consecutive blocks of l bits interleaved with zero bits, the modulation rules shown in Figure 6 are applied, and for the first group consisting of only / bits without zeros, The modulation rules shown in FIG. 9 are applied to the group. If the number M of consecutive / bits is (M≧5), then not only the inversion interval of T.

The modulation is performed so that an inversion interval of length JT and jT occurs. In this way, the frequency spectrum of the modulated signal is made up of only the inversion interval T and the color is lower than that of the recording amplifier.

This makes it easy to design a playback amplifier.

This modulation rule is based on the input data (
Z, A, B, C, D) and modulation signals (atb, c) are expressed by the following logical formula.

PI = c ・(A0B・(Q・(a+b)+a・b
・(i・(τ+5)+C−n−a))) P-total=A・[i・(π+100)+Q−(π+(τ+5)・
(c+b-p))] In the above formula, F is / when bit A is the nth / or (Hiroshi n+3)th / of consecutive /.

When the same input data as described above is modulated using such a modulation rule, the modulated signal becomes as shown in Figure 1, depending on whether the boundary is before or after the first 0. It is formed.

Furthermore, the modulation rule shown in FIG. 6 is applied to the first group in the same manner as described above, and the first modulation rule is applied to the second group.
The modulation rules shown in FIG. 2 may also be applied.

What is shown in FIG. 1 differs from FIG. 9 in that when the number M of consecutive /s is greater than or equal to three, the modulation is performed so that the signal rises from the starting position of the boundary. By doing so, the rate at which a pattern with an inversion interval T appears in a modulated signal can be reduced.

As shown in FIG. 13, Pl and Pl of the modulation signals are formed according to the following logical equations corresponding to bit A of consecutive bits (Z, A, B, C, D) of input data.

p, = b-(^1B-((Q+C'aD) ・(Z+a
)+Q-a-v・(τ+D))) P snow =A・ [100・ (Z+a)+Q ・ (100・
(C+D°)-(z+a-p)+z-a-b)) In the above formula, F is (41c)
/ when it is the n+co)th/or ('In+3)th l.

When input data similar to that shown in Fig. S is modulated using the modulation rule shown in Fig. 1, the 14th! As shown in the figure, a modulated signal with a waveform of λ can be obtained depending on whether the block boundary is set before or after 90, which appears first.

In the above explanation, O is the 70th value and / is the value of the building, but - this relationship may be reversed.

[Brief explanation of the drawing]

FIGS. 1 and 4 are waveform diagrams used to explain modulation rules in an embodiment of the present invention, and FIGS. 3 and 9 show the respective configurations of a modulation circuit and a demodulation circuit in an embodiment of the present invention. 5 is a waveform diagram showing an example of a modulation signal in one embodiment of the present invention; FIGS. 6 and 7 are waveform diagrams and route maps showing modulation rules in another embodiment of the invention; FIG. 9 is a waveform diagram showing an example of a modulation signal in another embodiment of the present invention, and FIGS. Figure 12, Figure 73, and Figure 1 are waveform diagrams and route maps used to explain the modulation method of the first embodiment of the present invention. 1.9...Shift register, 4.11...
...Combination circuit. Agent Masatomo Sugiura

Claims (1)

[Claims] A first group consisting of consecutive blocks of bits of the 10th value, sandwiched by λ bits of the bits of the 10th value, or bits of the 1st value; Divide the input data of the value code into the first group consisting of only bits, T, /jT#yuT,ko,
jT (T is the time of the 7th bit 13 of the input data)), and is the sum of the periods of the 1st O value and the sum of the periods of the 0th value in that block. The modulation #l for each of the seventh and third groups is made equal to
A digital modulation method characterized by modulating by jMI.