JPS57160240A - Error controller - Google Patents

Abstract

PURPOSE:To minimize transmission efficiency while holding the possibility of error overlooking within a prescribed range by estimating the error rate of a communication path, and setting it to the adequate number of corrected errors. CONSTITUTION:A received code 8 is converted by a receiving buffer 11 in bit- parallel and stored and its output is supplied to an error correcting circuit 12 to detect an error pattern to be corrected, which is sent to a buffer 13 for error pattern and a shift register 15. The output of the buffer 13 is supplied to an error bit counting circuit 14 to calculate the number of error bits, thereby outputting a signal 20 or 21 in accordance with the count value. The register 15 stores information on whether a prescribed number of past words outputed by the circuit 12 have a code error or not successively; and the number of words having code errors in the stored information is made by a deciding circuit 16 into threshold value information and when the number is below a prescribed value, the signal 22 is held at a 1. In response to an AND signal 23 of the signal 22 and the output of the circuit 14, a decoded code word synthesizing circuit 24 adds the outputs of the buffers 11 and 13 to output a corrected code 25. When the decision result of the circuit 16 is above the prescribed value, the transmitted signal 9 of an ARQ is outputted.