JPS5741050A - Code error correcting circuit - Google Patents
Code error correcting circuitInfo
- Publication number
- JPS5741050A JPS5741050A JP11660680A JP11660680A JPS5741050A JP S5741050 A JPS5741050 A JP S5741050A JP 11660680 A JP11660680 A JP 11660680A JP 11660680 A JP11660680 A JP 11660680A JP S5741050 A JPS5741050 A JP S5741050A
- Authority
- JP
- Japan
- Prior art keywords
- data
- code error
- case
- error rate
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
PURPOSE:To raise the efficiency of transmission of a data, by constituting so that the same frame is transmitted only once in case when a code error rate in trnsmitting a data is low, and the same frame is transmitted three times continuously in case when its code error rate is high. CONSTITUTION:A CPU8 decides whether a code error rate in case of transmitting a data is good or not, from a data of a result of check by a CRC circuit 7, and S/N in the data transmission line, etc. For instance, now, the CPU8 decides that the code error rate is low, and sets a mode so that 1 frame is transmitted only once. In this case, logic on a conductor 81 is inverted, and as a result, a switching circuit 9 outputs an output signal of a frame synchronization detecting circuit 1, and a gate circuit 10 outputs only a data part of a signal on a conductor 11, which is controlled by an output of the frame synchronization detecting circuit 1, and inputs it to a data buffer 6. On the other hand, in case when the code error rate is high, the CPU8 makes the logic on the conductor 81 different from said case, and sets it to a three continuous transmissions using shift registers 2a-3b and a deciding circuit 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11660680A JPS5741050A (en) | 1980-08-22 | 1980-08-22 | Code error correcting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11660680A JPS5741050A (en) | 1980-08-22 | 1980-08-22 | Code error correcting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5741050A true JPS5741050A (en) | 1982-03-06 |
Family
ID=14691320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11660680A Pending JPS5741050A (en) | 1980-08-22 | 1980-08-22 | Code error correcting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5741050A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4675867A (en) * | 1983-12-14 | 1987-06-23 | Canon Kabushiki Kaisha | Data processing device |
-
1980
- 1980-08-22 JP JP11660680A patent/JPS5741050A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4675867A (en) * | 1983-12-14 | 1987-06-23 | Canon Kabushiki Kaisha | Data processing device |
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