JPS57178451A - Code error detection system - Google Patents

Code error detection system

Info

Publication number
JPS57178451A
JPS57178451A JP6317381A JP6317381A JPS57178451A JP S57178451 A JPS57178451 A JP S57178451A JP 6317381 A JP6317381 A JP 6317381A JP 6317381 A JP6317381 A JP 6317381A JP S57178451 A JPS57178451 A JP S57178451A
Authority
JP
Japan
Prior art keywords
error detection
shifted
shift clock
constitution
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6317381A
Other languages
Japanese (ja)
Inventor
Masayuki Goto
Koji Nishizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6317381A priority Critical patent/JPS57178451A/en
Publication of JPS57178451A publication Critical patent/JPS57178451A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To enable code error detection with economical constitution by providing an exclusive OR circuit and a two-way shift resister which performs shifting to right or left according to whether an mBnB code is 1 or 0. CONSTITUTION:With a right shift clock, for example, ''1'' is shifted successively from a left end to right and with a left shift clock, ''0'' is shifted successively from a right end to left; when the ''1'' is shifted to a right-end output terminal RQ, its output signal is ''1'' and when the ''0'' is shifted to a left-end output terminal LQ, its output terminal is ''1''. When the running digital sum of an mBnB is between -l and +l, a two-way shift register 14 has 2l-stage constitution. An output signal from the RQ of the shift register 14 and the right shift clock are applied to an EXOR15, and an output signal from the LQ and the left shift clock are applied to an EXOR16, so that an error detection signal E is generated by ANDing the output of both the EXORs.
JP6317381A 1981-04-25 1981-04-25 Code error detection system Pending JPS57178451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6317381A JPS57178451A (en) 1981-04-25 1981-04-25 Code error detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6317381A JPS57178451A (en) 1981-04-25 1981-04-25 Code error detection system

Publications (1)

Publication Number Publication Date
JPS57178451A true JPS57178451A (en) 1982-11-02

Family

ID=13221598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6317381A Pending JPS57178451A (en) 1981-04-25 1981-04-25 Code error detection system

Country Status (1)

Country Link
JP (1) JPS57178451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100322574B1 (en) * 1998-07-01 2002-03-08 윤종용 How to generate error detection code

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100322574B1 (en) * 1998-07-01 2002-03-08 윤종용 How to generate error detection code

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