JPH0652008A - Edc lsi checking device - Google Patents

Abstract

PURPOSE:To confirm an normal operation of a general purpose EDC LSI by a simple hardware constitution. CONSTITUTION:An EDC bit inversion control part 9 transmits alternately an output enable signal to a data 1-bit, inverting part 15 and a data 2-bit inverting part 16 so that data subjected to 1-bit 2-bit inversion is sent to an EDC LSI 3, and a central control processor 17 executes a read-out operation to a main storage device 1. The main storage device 1 transmits the data subjected to 1-bit or 2-bit inversion to the EDC LSI 3 by the data 1-bit inverting part 15 or the data 2-bit inverting part 16. The EDC LSI 13 transmits 1-bit, 2-bit error report signals 6, 7 to a register 8, when a bit error detecting circuit 4 receives the data subjected to 1-bit, 2-bit inversion, and the register 8 confirms a fact that a 1-bit, 2-bit error detecting circuit is operating normally.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a general-purpose EDC LSI (E
error Detection and Correc
(ion LSI) memory data error detection / correction circuit.

[0002]

2. Description of the Related Art Conventionally, in a memory data error detection / correction circuit using a general-purpose EDC LSI, a general-purpose EDC LSI is connected between a main bus and a memory section, and the general-purpose EDC LSI transfers data during a read operation of the memory section. Error detection and correction were performed.

If a general-purpose EDC LSI does not detect a data error, it sends the data as it is to the main bus, and the data 1
When a bit error is detected, the general-purpose EDC LSI corrects the error bit and sends the data to the main bus to notify the 1-bit error / 2-bit error report register that there is a 1-bit error, and the data 2-bit error. When detected, the 1-bit error / 2-bit error report register was notified that it was a 2-bit error.

[0004]

This conventional general-purpose EDC
The error detection / correction circuit for memory data using the LSI has a problem that there is no means for confirming whether the general-purpose EDC LSI is a defective product or has failed.

[0005]

EDC LSI of the present invention
The check device includes a main storage device that stores data, a central control processing device that controls reading of data from the main storage device, a general-purpose EDC LSI, and the general-purpose EDC LS.
A register for holding a data bit error report signal from I, a normal data transmitting section in normal operation, a data bit inverting section for inverting the data bit of the data from the main storage device, and data of the normal data transmitting section An EDC bit inversion control unit for performing transmission control and data bit inversion control of the data bit inversion unit, and the general-purpose ED
The C LSI receives the data read from the main storage device and the bit-inverted data from the data bit inversion unit, and transmits the data bit error report signal to the register. A 1-bit error correction circuit for correcting a bit error is provided.

The data bit inversion unit inverts the data from the main memory by 1 bit, 2
It comprises a data 1-bit inversion unit and a data 2-bit inversion unit for performing bit inversion, and the EDC bit inversion control unit alternately sends an enable signal to the data 1-bit inversion unit and the data 2-bit inversion unit for control. And
Further, the bit error detection circuit inputs the 1-bit inverted data and 2-bit inverted data and outputs a 1-bit error report signal and a 2-bit error report signal. Further, the general-purpose EDC LSI includes a 1-bit error correction circuit that performs error correction of the 1-bit error data from the bit error detection circuit, and the central control processing unit includes the normal data from the normal data transmission unit and the 1-bit error correction circuit. It is characterized in that a comparison check is performed with the corrected data output from the error correction circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the EDC LSI check device of the present invention.

In this embodiment, a main memory device 1 for storing data, a general-purpose EDC LSI (hereinafter simply referred to as EDC LSI) 3, a data bus 2 for connecting the main memory device 1 and the EDC LSI 3, and an EDC LSI 3 are used. The register 8 for holding the 1-bit error report signal 6 and the 2-bit error report signal 7, the normal data transmitter (bus buffer) 14 in the normal operation, and the 1-bit and 2-bit data from the main memory 1 A normal data output enable signal to the data 1-bit inversion unit (inverter) 15, the data 2-bit inversion unit (inverter) 16, the normal data transmission unit 14, the data 1-bit inversion unit 15, and the data 2-bit inversion unit 16 which are respectively inverted. 10, activate the data 1-bit inverted output enable signal 11 and the data 2-bit inverted output enable signal 12 EDC bit inversion control unit 9 for controlling the data and a central control processing unit 17 for sending a read signal 18 to the main memory 1 to read the data.
The DC LSI 3 includes a bit error detection circuit 4 that detects a 1-bit error / 2-bit error of the data read from the main storage device 1 and a 1-bit error correction circuit 5 that corrects the 1-bit error.

Next, the operation of this embodiment will be described.
In confirming the normal operation of the general-purpose EDC LSI, the central control processing unit 17 first performs a read operation with respect to the main storage device 1. At this time, the EDC bit inversion control unit 9 transmits the normal data output enable signal 10 to the normal data transmission unit 14, and the data in the main storage device 1 is directly transmitted through the data bus 2, EDC LSI 3, and main data bus 13. It is read by the central control processing unit 17.

Next, the EDC bit inversion control section 9 alternates the data 1 bit inversion section 15 with the data 1 bit inversion output enable signal 11 and the data 2 bit inversion section 16 with the data 2 bit inversion output enable signal 12 alternately. Sent to EDC and 1-bit or 2-bit inverted data is EDC
After being sent to the LSI 3, the central control processing unit 17 performs a read operation to the main memory 1. The main storage device 1 that has received the read operation is processed by the data 1-bit inversion unit 15 or the data 2-bit inversion unit 16 to perform EDC.
1 bit inverted data for LSI3 or 2
Send the bit-reversed data. In the EDC LSI 3, when the bit error detection circuit 4 inverts 1 bit and receives the data, the 1 bit error report signal 6 is received, and when the bit error detection circuit 4 receives the inverted data, the 2 bit error report signal 7 is received.
To the register 8 and the register 8 can confirm that the 1-bit or 2-bit error detection circuit is operating normally.

The 1-bit error data is error-corrected by the 1-bit error correction circuit 5, and the main data bus 1
3 to the central control processing unit 17. This corrected data is compared with the data previously transmitted through the normal data transmission unit 14, and if the data is the same, then 1
It can be confirmed that the bit error correction circuit 5 is operating normally.

[0012]

As described above, according to the present invention, the bit inversion unit and the bit inversion control unit are configured by hardware between the main storage device and the general-purpose EDC LSI without providing an error data area in the main storage device in advance. By doing so, it is possible to easily confirm the normal operation of the EDC LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an EDC LSI check device of the present invention.

[Explanation of symbols]

 1 main memory 2 data bus 3 general purpose EDC LSI 4 bit error detection circuit 5 1 bit error correction circuit 6 1 bit error report signal 7 2 bit error report signal 8 register 9 EDC bit inversion control unit 10 normal data output enable signal 11 data 1-bit inverted output enable signal 12 data 2-bit inverted output enable signal 13 Main data bus 14 Normal data transmission unit 15 Data 1-bit inversion unit 16 Data 2-bit inversion unit 17 Central control processing unit 18 Read signal

Claims (4)

[Claims] 1. A main memory device for storing data, a central control processing device for controlling data reading from the main memory device, a general-purpose EDC LSI, and the general-purpose EDC LS.
A register for holding a data bit error report signal from I, a normal data transmitting section in normal operation, a data bit inverting section for inverting the data bit of the data from the main storage device, and data of the normal data transmitting section An EDC bit inversion control unit for performing transmission control and data bit inversion control of the data bit inversion unit, and the general-purpose ED
The C LSI receives the data read from the main storage device and the bit-inverted data from the data bit inversion unit, and transmits the data bit error report signal to the register. An EDC LSI check device comprising a 1-bit error correction circuit for correcting a bit error. 2. The data bit inverting unit comprises a data 1-bit inverting unit and a data 2-bit inverting unit that perform 1-bit inverting and 2-bit inverting of the data from the main storage device, respectively, and the EDC bit inverting control unit. The control is performed by alternately sending an enable signal to the data 1-bit inversion unit and the data 2-bit inversion unit.
EDC LSI check device described. 3. The bit error detection circuit inputs the 1-bit inverted data and the 2-bit inverted data and outputs a 1-bit error report signal and a 2-bit error report signal. EDC of 2
LSI check device. 4. The general-purpose EDC LSI includes a 1-bit error correction circuit that performs error correction of 1-bit error data from the bit error detection circuit, and the central control processing unit stores the normal data from the normal data transmission unit. 2. The EDC according to claim 1, wherein the EDC is compared and checked with the corrected data output from the 1-bit error correction circuit.
LSI check device.