JPH02113341A - Error correction system - Google Patents

Abstract

PURPOSE:To increase the possibility of error correction by inverting the bit which has the highest possibility of an error at the time of demodulation and using the decoding result when the error which can not be corrected is generated. CONSTITUTION:A demodulator 1 demodulates a single error correction, double error detection code (SEC/DED code) and sends it out to a 1st decoder 1 through a signal line 6 and when demodulation is performed, one bit between bits 0 and 1 of a voltage closest to a threshold voltage for 0/1 bit decision making is inverted and sent out to the 2nd decoder 3 through a signal line 7. A selecting circuit 4 sends a signal indicating that an error is detected, but can not be corrected to the system through a signal line 13 while outputting the SEC/DED code decoded by the decoder 2 from a signal line 12 when both the decoders 2 and 3 detect the error which can not be corrected. Consequently, the possibility of error correction when the error which can not be corrected, but can be detected is generated is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction method for an error correction code, and particularly to a method for correcting an error when an error that cannot be corrected but is detectable occurs.

[Prior Art] Conventionally, the error correction method for this type of random error correction block code only raises an error detection signal when an error that can be detected but cannot be corrected occurs. Then, the system recognized the error detection and performed a data transfer trial process. Furthermore, some audio information, image information, etc. are provided with a mechanism for estimating from the correlation between the front and back.

[Problems to be Solved by the Invention] In the conventional error correction method described above, when an error that cannot be corrected and that can be detected occurs in the system error correction block code, it is necessary to simply raise the error detection signal. Therefore, the system has no choice but to perform data transfer trial processing, which has the drawback of reducing data transfer throughput. Furthermore, the technique of determining a code from previous and subsequent estimates using audio information or image information has the drawback that the information of the code itself is not necessarily reflected correctly.

[Means for Solving the Problems] The error correction method according to the present invention is based on the random error Jf before demodulation input in bit serial.
The correct block code is demodulated, and the first demodulated signal and the bit with the voltage value closest to the threshold voltage for determining whether the bit is 0 or 1 in the block during demodulation are inverted by 0 or 1 by one bit. a demodulator that bit-serially outputs a second demodulated signal; and a demodulator that decodes the first demodulated signal;
a first decoder that outputs a first decoded code subjected to error correction and a first error detection signal indicating that error correction has been performed but error correction is not possible; a second decoder that decodes code j and outputs a second decoded code subjected to error correction and a second error detection signal indicating that error correction has been performed but error correction is not possible; and, if the first error detection signal is not received, the first decoded code is received, but the first error detection signal is not received,
If the second error detection signal is not received, the second decoded code is transmitted together with the first decoded code if both the first and second error detection signals are received. The present invention is characterized in that it has a selection circuit that outputs a signal indicating that +ai error has been detected although it is impossible to correct an error, as a selected signal.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. As an example, a single error correction/double error detection code (hereinafter referred to as SEC/DED code) is used.

An example is an extended Hamming code. ) error correction method.

This circuit includes a demodulator 1 and first and second decoders 2, 3.
and a selection circuit 4 for the codes decoded by the first and second decoders, and between the demodulator 1 and the first decoder 2 is a signal line 6 for the demodulated SEC/DED code, and second
The decoder 3 is connected to the signal line 7 of the SEC/DED code, which is obtained by inverting and demodulating the bits 0 and 1 having the voltage value closest to the threshold voltage for determining bit 0.1 during demodulation.

Further, the first and second decoders 2 and 3 and the selection circuit 4 are connected to a signal line 8.9 of the decoded SEC/DED code, and a signal line 10 indicating that an error has been detected but cannot be corrected.
．． 11.

Further, the input signal line 5 of the SEC/DED code before demodulation is connected to the demodulator 1, and the selection circuit 4 is connected to the input signal line 5 of the SEC/DED code before demodulation.
A signal line 13 indicating that an error has been detected but cannot be corrected is tangent to the output signal line 12 of the DED code.

Next, the operation of the error correction system of the circuit of this embodiment configured as described above will be explained.

The SEC/DED code before demodulation is input to the m modulator 1 in a bit-serial manner via an input signal line 5.

The demodulator 1 performs the following two operations.

1) Demodulate the SEC/DED code and send the code bit serially to the first decoder 2 via the signal line 6.

2) At the same time as demodulating the SEC/DED code, 0.1 of the bit whose voltage is closest to the threshold voltage for determining 0.1 of the bit during demodulation is inverted by one bit and sent to the decoder 3 via the signal line 7. The code is transmitted bit serially.

The first decoder 2 and the second decoder 3 perform error correction processing and error detection processing, and send the decoded SEC/DED code to the selection circuit 4 via signal lines 8 and 9 in a bit serial manner. Furthermore, if an error is detected but the error cannot be corrected, the selection circuit 4 is notified via the signal line 10.11.

The selection circuit 4 performs the following operations.

l) If the first decoder does not detect an uncorrectable error, the SEC/DED code decoded by the first decoder is output bit-serial from the signal line 12.

2) The first decoder detects an uncorrectable error, and the second
If the second decoder does not detect an uncorrectable error, the SEC/DED code decoded by the second decoder is output bit serially from the signal line 12.

3) If both the first decoder and the second decoder detect an uncorrectable error, the S decoded by the first decoder
At the same time, the EC/DED code is output bit-serial from the signal line 12, and at the same time, a notification is sent to the system via the signal line 13 indicating that an error has been detected but cannot be corrected.

[Effects of the Invention] As explained above, in the present invention, when an error occurs that can be detected but cannot be corrected, the bit most likely to be in error is inverted during demodulation, and then Using the decoded results has the effect of increasing the possibility of error correction. Furthermore, this makes it possible to reduce the number of data transfer try processes, which has the effect of improving data transfer throughput. Furthermore, for blocks that cannot be corrected due to audio information, image information, etc., the information in the code itself can be more accurately reflected by decoding the code, compared to methods that have a mechanism that estimates from the correlation between the front and back. There is an effect that can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a circuit to which an error correction method according to an embodiment of the present invention is applied. 1... Demodulator, 2... First decoder, 3... Second
decoder, 4... selection circuit, 5... SEC before demodulation
/DED code input signal line, 6... demodulated SEC
/DED code signal line, 7...During demodulation, bit 0°1
The signal line of the SEC/DED code in which 0.1 of the bit of the voltage closest to the threshold voltage is inverted, 8.9...
Signal line of decoded SEC/DED code, 10.11.
...Signal line indicating that an error has been detected but cannot be corrected, 12...Output signal line of the decoded SEC/DED code, 13...Signal line that indicates that an error has been detected but cannot be corrected. Signal line shown.

Claims (1)

[Claims] 1. Demodulating the random error correction block code before demodulation that is input bit serially, and a first demodulated signal;
During demodulation, the bit with the voltage value closest to the threshold voltage for determining whether the bit is 0 or 1 in the block is set to 0 or 1.
a demodulator that outputs a second demodulated signal obtained by inverting the first demodulated signal in a bit-serial manner; a first decoded code that decodes the first demodulated signal and performs error correction; a first error detection signal indicating that the error cannot be corrected;
a second decoded code that decodes the second demodulated signal and performs error correction, and a second error detection signal indicating that error correction has been performed but error correction is not possible. The second output
a decoder that receives the first decoded code if the first error detection signal is not received;
If the second error detection signal is not received, the second decoded code is transmitted together with the first decoded code if both the first and second error detection signals are received. 1. An error correction method for a block code capable of error correction and error detection, comprising a selection circuit that outputs a signal indicating that an error is detected but cannot be corrected as a selected signal.