JP2001251197A - Error correction receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that errors of two or move bits cannot be corrected in a conventional error correction receiver receiving a Hamming- encoded signal since a Hamming code is a one bit error correction code. SOLUTION: An error correction receiver is provided with a synchronism detection means which receives a Hamming-encoded signal on a transmission side and synchronously detects a reception signal, a judgement means for judging the signal of the output of the synchronism detection means by a prescribed threshold, a differential decoding means for obtaining the change of the output of the judgement means for one symbol, a division means for dividing the output of the differential decoding means by a prescribed generated polynomial and obtaining a remainder and an error correction means which corrects the error of the output of the differential decoding means in accordance with the value of the remainder being the output of the division means, and the receiver receives Hamming-encoded signals. Even if continuous two bits are erroneous, the error can be corrected by a Hamming code being a one bit error correction code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction receiver for receiving a Hamming-coded signal.

[0002]

2. Description of the Related Art In digital signal transmission, a signal may be erroneously determined on the receiving side depending on the environment of the transmission path. If an error occurs, the receiving sensitivity deteriorates. A known method for correcting this error is an error correction code for correcting an error by adding a redundant bit to an information bit. Here, the Hamming code is known as an error correction code for correcting a one-bit error.

FIG. 5 is a block diagram of a conventional error correction receiver for receiving a Hamming-coded signal.

As shown in FIG. 5, an error correction receiver demodulates a received signal and determines the demodulated signal, a division circuit 2 which divides an input signal by a predetermined generator polynomial to obtain a remainder, and a division circuit 2 An error correction circuit 3 that corrects an error of the determination signal output from the demodulation circuit 1 according to the remainder is provided.

FIG. 6 is an explanatory diagram of an example of a Hamming code in the error correction receiver.

[0006] One block shown is composed of 4 information bits,
Consider a Hamming (7,4) code composed of three check bits. The generating polynomial of this Hamming code is expressed by (Equation 1)
And

[0007]

(Equation 1)

[0008] The four information bits are changed to (a0, a1, a
2, a3), the calculation is 0 + 0 = 0, 0 + 1 = 1, 1,
Assuming that the method 2 is performed with + 0 = 1 and 1 + 1 = 0,
When (Equation 2) is divided by a generator polynomial, the remainder becomes (Equation 3),
This remainder is added as a check bit.

[0009]

(Equation 2)

[0010]

(Equation 3)

From this, the check bits (a4, a5, a6)
Becomes the following (Equation 4), (Equation 5), and (Equation 6). The transmission code sequence (Equation 7) to which the remainder of the division by the generator polynomial is added is divisible by the generator polynomial if there is no error on the receiving side, and cannot be divided if an error occurs.

[0012]

(Equation 4)

[0013]

(Equation 5)

[0014]

(Equation 6)

[0015]

(Equation 7)

For example, when a0 is incorrect, the remainder becomes (Equation 8) from (Equation 3).

[0017]

(Equation 8)

This residual coefficient vector ((a0 + a1 +
a2), (a1 + a2 + a3), (a0 + a1 + a
3)) is called a syndrome. For example, when only a0 is incorrect, it is described as 101.

FIG. 7 is an explanatory diagram of the relationship between syndromes and error bits when the Hamming code of FIG. 6 is used.

As shown in FIG. 7, since each syndrome is different for a one-bit error, an error bit can be specified and the error can be corrected.

[0021]

When the differential synchronous detection is used as the detection method, the demodulation circuit has a configuration as shown in FIG. That is, a configuration including a synchronous detection circuit 4 for synchronously detecting a received signal, a determination circuit 5 for performing data determination using a predetermined threshold value, and a differential decoding circuit 6 for determining a change between one symbol. Become.

Next, FIG. 9 is an explanatory diagram showing how data is reproduced by differential decoding in the error correction receiver.
On the transmitting side, differential encoding is performed in order to transmit a change in the information signal. After the signal determination, the receiving side performs differential encoding for detecting a change in information between one symbol to obtain information data. If there is no error, the data after differential decoding matches the information signal on the transmission side as shown in FIG. However, when an error exists as shown in FIG.
One bit error at the output of the decision circuit is 2
It becomes an error consecutively for bits. Since the Hamming code is a one-bit error correction code, it cannot correct an error of two bits or more.

The present invention solves the above-mentioned conventional problems, and provides an error correction receiver capable of correcting a Hamming-coded signal even when two bits are erroneous by using differential synchronous detection as a detection method. It is intended to be.

[0024]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a synchronous detection means for receiving a Hamming-encoded signal on a transmission side and synchronously detecting a received signal, and an output of the synchronous detection means. Determining means for determining a signal based on a predetermined threshold value; differential decoding means for obtaining a change in the output of the determining means between one symbol; and a remainder obtained by dividing the output of the differential decoding means by a predetermined generator polynomial. An error correction receiver having a configuration including a dividing unit to be obtained and an error correcting unit for correcting an error of the output of the differential decoding unit according to a remainder value output from the dividing unit.

According to the present invention, in an error correction receiver for receiving a Hamming-encoded signal, by using differential synchronous detection, even when two consecutive bits are erroneous, a one-bit error correction code can be used. An error can be corrected by a certain Hamming code, and the receiving sensitivity can be improved.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a synchronous detecting means for receiving a signal subjected to Hamming encoding on a transmitting side and synchronously detecting a received signal, and outputting the output of the synchronous detecting means to a predetermined level. Determining means for determining a signal based on a threshold value;
A differential decoding means for obtaining a change in one symbol between outputs of the determination means, a division means for dividing the output of the differential decoding means by a predetermined generator polynomial to obtain a remainder, and a difference according to a remainder value which is an output of the division means. An error correction receiver having an error correction means for correcting an error of an output of a dynamic decoding means, and has an effect that even if two bits are erroneous, an error can be corrected by a Hamming code.

According to a second aspect of the present invention, in the error correction receiver according to the first aspect, the error correction means comprises:
When a set of information bits and check bits is regarded as one block, error correction is performed in accordance with the remainder value output from the dividing means of the block and the preceding and following blocks. In this case, correction is performed continuously for two bits, so that even if a two-bit error occurs, the error can be corrected by the Hamming code.

According to a third aspect of the present invention, in the error correction receiver according to the first aspect, the error correction means comprises:
When a set of information bits and check bits is regarded as one block, error correction is performed in accordance with the remainder value output from the dividing means of the block and the preceding and following blocks. In this case, since two bits are continuously corrected, an error can be corrected by the Hamming code even if two bits are erroneous.

According to a fourth aspect of the present invention, in the error correction receiver according to the first aspect, the error correction means comprises:
The correction according to claims 2 and 3 is performed, and has an effect that even if two bits are erroneous, the error can be corrected by the Hamming code.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of an error correction receiver according to Embodiment 1 of the present invention, and FIG. 2 is an explanatory diagram of an example of a Hamming code in the error correction receiver.

As shown in FIG. 1, the error correction receiver includes a synchronous detection circuit 7 for synchronously detecting a received signal, a determination circuit 8 for performing data determination using a predetermined threshold value, and a change of one symbol. , A division circuit 10 for dividing by a predetermined generator polynomial to find a syndrome, and an error for correcting an error in the output signal of the differential decoding circuit 9 in accordance with the value of the syndrome found by the division circuit 10. Correction circuit 11
It is provided with.

FIG. 2 shows an example of the Hamming code.
Consider a Hamming (7,4) code in which one block is composed of 4 information bits and 3 check bits as shown in FIG. Let the generator polynomial of this Hamming code be (Equation 1).

Only one bit in one block can be corrected by the syndrome obtained by the division circuit 10. However, in the differential synchronous detection, the probability that only one bit is erroneous is low, and the probability that two consecutive bits are erroneous is high. Therefore, by performing continuous two-bit error correction according to the syndrome obtained by the division circuit 10 as shown in FIG. Correction can be performed, and reception sensitivity can be improved.

(Embodiment 2) FIG. 3 is an explanatory diagram of an error correction method in an error correction receiver according to Embodiment 2 of the present invention. As an example of the Hamming code, consider a Hamming (7, 4) code in which one block shown in FIG. 6 is composed of 4 information bits and 3 check bits. Let the generator polynomial of this Hamming code be (Equation 1).

In the second embodiment, when differential synchronous detection is used as the detection method, it is conceivable that two consecutive bits are erroneous, and an error occurs between blocks as shown in FIG. As shown in FIG. 3, three continuous blocks are defined as b0, b1, and b2. Considering b1, two patterns are conceivable as a pattern which is erroneous over blocks. In the division circuit 10, 3
By obtaining the syndromes of two blocks and performing error correction in the error correction circuit 11 in consideration of the syndromes of the preceding and succeeding blocks, it is possible to correct a continuous two-bit error straddling between the blocks and improve the reception sensitivity. For example, if (a06, a10) is incorrect, b
The syndrome of 0 is 001 and the syndrome of b1 is 10
In the case where (a16, a20) is erroneous, the syndrome of b1 is 001 and the syndrome of b2 is 101, so that an error bit can be specified, and the error correction circuit 11 corrects the error. The receiving sensitivity can be improved.

(Embodiment 3) FIG. 4 is an explanatory diagram of an error correction method in an error correction receiver according to Embodiment 3 of the present invention. As an example of the Hamming code, consider a Hamming (7, 4) code in which one block shown in FIG. 6 is composed of 4 information bits and 3 check bits.

In the third embodiment, the syndrome of three consecutive blocks b0, b1, and b2 is obtained by the division circuit 10. The error correction circuit 11 corrects the error of the block b1 according to the relationship between the syndromes before and after shown in FIG. B if the syndrome is 001 or 101
Since it cannot be determined whether there are two consecutive errors in one block or an error between blocks,
An error bit is specified by dividing the case from b0 of the immediately preceding block and the syndrome of the immediately following block. By performing error correction based on not only the syndrome of the block for which error correction is performed but also the syndrome of the preceding and following blocks, not only consecutive 2-bit errors in a block but also errors between blocks can be corrected. Sensitivity can be improved.

[0039]

As is apparent from the above description, according to the present invention, by using differential synchronous detection, two consecutive
Even when a bit is erroneous, an advantageous effect is obtained that an error correction receiver that can correct an error by a Hamming code, which is a one-bit error correction code, and improve reception sensitivity can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an error correction receiver according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of a Hamming code in the error correction receiver.

FIG. 3 is an explanatory diagram of an error correction method in an error correction receiver according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of an error correction method in an error correction receiver according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a conventional error correction receiver for receiving a Hamming-coded signal.

FIG. 6 is an explanatory diagram of an example of a Hamming code in the error correction receiver.

FIG. 7 is an explanatory diagram of a relationship between a syndrome and an error bit when the Hamming code of FIG. 6 is used.

FIG. 8 is a block diagram of a demodulation circuit using differential synchronous detection in the error correction receiver.

FIG. 9 is an explanatory diagram of how data is reproduced by differential decoding in the error correction receiver.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 demodulation circuit 2 division circuit 3 error correction circuit 4 synchronous detection circuit 5 determination circuit 6 differential decoding circuit 7 synchronous detection circuit 8 determination circuit 9 differential decoding circuit 10 division circuit 11 error correction circuit

Claims (4)

[Claims] 1. A synchronous detecting means for receiving a Hamming-encoded signal on a transmitting side and synchronously detecting a received signal, a determining means for judging a signal based on a predetermined threshold value of an output of the synchronous detecting means, Differential decoding means for calculating a change between one symbol of the output of the determination means, division means for dividing the output of the differential decoding means by a predetermined generator polynomial to obtain a remainder, and calculating a remainder value which is the output of the division means. An error correction receiver comprising an error correction means for correcting an error of the output of the differential decoding means in response. 2. The error correction means according to claim 1, further comprising:
2. The error correction receiver according to claim 1, wherein correction is performed continuously for bits. 3. The error correction means, assuming that a set of information bits and check bits is one block, perform error correction according to the remainder of the output of the division means of the block and the preceding and following blocks. Claim 1.
Error correction receiver as described. 4. The error correction receiver according to claim 1, wherein the error correction means performs the correction according to claims 2 and 3.