JPS6089700U - memory circuit - Google Patents
memory circuitInfo
- Publication number
- JPS6089700U JPS6089700U JP18117483U JP18117483U JPS6089700U JP S6089700 U JPS6089700 U JP S6089700U JP 18117483 U JP18117483 U JP 18117483U JP 18117483 U JP18117483 U JP 18117483U JP S6089700 U JPS6089700 U JP S6089700U
- Authority
- JP
- Japan
- Prior art keywords
- storage element
- binary logic
- memory circuit
- logic storage
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例に係る読み出し誤り検出機能を有する記
憶回路の構成を示すブロック図、第２図は本考案の実施
例に係る読み出（誤り検出機能を有する記憶回路の構成
を示すブロック図である。
１．１’、１″・・・二値論理記憶素子、６・・・偶奇
性一致監視回路、９・・・監視回路、１０・・・排他的
論理和回路、１Ｆ・・論理和回路。FIG. 1 is a block diagram showing the configuration of a storage circuit having a read error detection function according to a conventional example, and FIG. 2 is a block diagram showing the configuration of a storage circuit having a read (error detection function) according to an embodiment of the present invention. 1.1', 1''... Binary logic storage element, 6... Parity/oddness matching monitoring circuit, 9... Monitoring circuit, 10... Exclusive OR circuit, 1F... Logic sum circuit.
Claims (1)
を有し、同一のアドレスには同一のデータが記憶されて
いる第２の二値論理記憶素子と、アドレス指定により読
み出された前記第１の二値論理記憶素子の記憶データと
前記第２の二値論理記憶素子の記憶データの対応するビ
ットごとにその論理状態の同一性を検知する読み出し誤
り監視回路とによって構成されたことを特徴とする記憶
回路。[Claims for Utility Model Registration] A first binary logic storage element having a common address/line with the first binary logic storage element, and the same data is stored at the same address. a second binary logic storage element, and the logic of each corresponding bit of the storage data of the first binary logic storage element and the storage data of the second binary logic storage element read out by addressing. 1. A memory circuit comprising: a read error monitoring circuit for detecting the sameness of states.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18117483U JPS6089700U (en) | 1983-11-24 | 1983-11-24 | memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18117483U JPS6089700U (en) | 1983-11-24 | 1983-11-24 | memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6089700U true JPS6089700U (en) | 1985-06-19 |
Family
ID=30392654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18117483U Pending JPS6089700U (en) | 1983-11-24 | 1983-11-24 | memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089700U (en) |
-
1983
- 1983-11-24 JP JP18117483U patent/JPS6089700U/en active Pending
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