JPH0280366U

JPH0280366U -

Info

Publication number: JPH0280366U
Application number: JP15705288U
Authority: JP
Priority date: 1988-12-01
Filing date: 1988-12-01
Publication date: 1990-06-20

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の主要部の構成を示
すブロツク図、第２図は第１図のクロツクビツト
チエツク回路の詳細な回路図、第３図はＭＦＭ記
録方式におけるクロツクビツトの書き込み条件を
示す図表、第４図及び第５図は第２図の回路の動
作波形を示す図である。１……データセパレータ、７……クロツクビツ
トチエツク回路。 Fig. 1 is a block diagram showing the configuration of the main part of an embodiment of the present invention, Fig. 2 is a detailed circuit diagram of the clock bit check circuit of Fig. 1, and Fig. 3 is a block diagram showing the clock bit check circuit of Fig. 1. The charts showing the conditions, FIGS. 4 and 5, are diagrams showing the operating waveforms of the circuit of FIG. 2. 1...Data separator, 7...Clock bit check circuit.

Claims

[Claims for Utility Model Registration] In a magnetic storage device having means for reading signals from a magnetic recording medium, data bit detection means for detecting data bits in the signals to be read out, and clock bits in the signals to be read out. a clock bit detection means; and an error determination unit that determines whether a relationship between a data bit detected by the data bit detection means and a clock bit detected by the clock bit detection means satisfies a predetermined condition, and determines a clock bit error. An error detection circuit in a magnetic storage device, comprising: means.