JPS6145771U - Data recorder with verification function - Google Patents

Data recorder with verification function

Info

Publication number
JPS6145771U
JPS6145771U JP12838184U JP12838184U JPS6145771U JP S6145771 U JPS6145771 U JP S6145771U JP 12838184 U JP12838184 U JP 12838184U JP 12838184 U JP12838184 U JP 12838184U JP S6145771 U JPS6145771 U JP S6145771U
Authority
JP
Japan
Prior art keywords
data signal
read head
output signal
data recorder
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12838184U
Other languages
Japanese (ja)
Inventor
正 佐々木
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP12838184U priority Critical patent/JPS6145771U/en
Publication of JPS6145771U publication Critical patent/JPS6145771U/en
Pending legal-status Critical Current

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  • Digital Magnetic Recording (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例の回路図である。 〜ＶＨ・・・書込みヘッド、ＲＨ・・・読出しヘッド、
ＩＮ・・・データ信号入力端子、１・・・記録媒体、２
・・・遅延回路、３・・・Ｆ−Ｖ変換器、１０・・・比
較回路。FIG. 1 is a circuit diagram of an embodiment of the present invention. ~VH...Writing head, RH...Reading head,
IN...Data signal input terminal, 1...Recording medium, 2
... Delay circuit, 3... F-V converter, 10... Comparison circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ信号入力端子に増幅器を介して接続され入力テー
タ信号を記録媒体に書込む書込みヘッドと、前記記録媒
体の進行方向に関して前記書込みヘッドの前方に設けた
読出したヘッドと、この読出しヘッドの出力信号の周波
数を電圧に変換するＦ−Ｖ変換器と、前記データ信号入
力端子に接続され前記Ｆ−Ｖ変換器の出力によって遅延
時間を制御され前記入力データ信号に遅延を与える遅延
回路と、この遅延回路の出力信号と前記読出しヘツドの
出力信号との一致を求め不一致の度合いを規定の閾値と
比較して表示または出力する比較回路とを備えたことを
特徴とす葛ベリファイ機能付きデータレコーダ。a write head connected to a data signal input terminal via an amplifier to write an input data signal onto a recording medium; a read head provided in front of the write head with respect to the traveling direction of the recording medium; and an output signal of the read head. a delay circuit connected to the data signal input terminal and having a delay time controlled by the output of the F-V converter to delay the input data signal; What is claimed is: 1. A data recorder with a single-verify function, comprising a comparison circuit that determines the coincidence between the output signal of the circuit and the output signal of the read head, compares the degree of mismatch with a prescribed threshold value, and displays or outputs the result.
JP12838184U 1984-08-24 1984-08-24 Data recorder with verification function Pending JPS6145771U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12838184U JPS6145771U (en) 1984-08-24 1984-08-24 Data recorder with verification function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12838184U JPS6145771U (en) 1984-08-24 1984-08-24 Data recorder with verification function

Publications (1)

Publication Number Publication Date
JPS6145771U true JPS6145771U (en) 1986-03-26

Family

ID=30687009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12838184U Pending JPS6145771U (en) 1984-08-24 1984-08-24 Data recorder with verification function

Country Status (1)

Country Link
JP (1) JPS6145771U (en)

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