JPS6374800U - - Google Patents
Info
- Publication number
- JPS6374800U JPS6374800U JP16954286U JP16954286U JPS6374800U JP S6374800 U JPS6374800 U JP S6374800U JP 16954286 U JP16954286 U JP 16954286U JP 16954286 U JP16954286 U JP 16954286U JP S6374800 U JPS6374800 U JP S6374800U
- Authority
- JP
- Japan
- Prior art keywords
- access time
- timing corresponding
- memory
- data
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の実施例を示す回路ブロツク図
、第２図はその動作タイミングを示す図、第３図
は従来例の構成を示す回路ブロツク図、第４図は
その動作タイミングを示す図である。
１……メモリ、２……比較回路（ＥＸーＵｏＲ
）、３……アンドゲート、１２……Ｄタイプフリ
ツプフロツプ。
FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing its operation timing, FIG. 3 is a circuit block diagram showing the configuration of a conventional example, and FIG. 4 is a diagram showing its operation timing. It is. 1...Memory, 2...Comparison circuit (EX- Uo R
), 3...AND gate, 12...D type flip-flop.
Claims (1)
ータを規定のアクセス時間に相当するタイミング
にて比較しその比較結果により判定が行なわれる
ものであつて、上記比較を行なう比較回路と、こ
の比較回路により出力される信号と上記アクセス
時間に相当するタイミングで供給されるチエツク
信号が入力され両者の論理積条件をとつてメモリ
のアクセス時間が規定のアクセス時間を超えたこ
とを検出するアンドゲートと、このゲート出力が
ラツチされ、異常を通知するフリツプフロツプと
を具備することを特徴とするチエツク回路。 The read data and the data to be written into the memory are compared at a timing corresponding to a specified access time, and a judgment is made based on the comparison result. An AND gate which receives an output signal and a check signal supplied at a timing corresponding to the above-mentioned access time, calculates the AND condition of the two, and detects that the memory access time has exceeded the specified access time; A check circuit characterized in that it is equipped with a flip-flop whose gate output is latched and which notifies an abnormality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16954286U JPS6374800U (en) | 1986-11-06 | 1986-11-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16954286U JPS6374800U (en) | 1986-11-06 | 1986-11-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6374800U true JPS6374800U (en) | 1988-05-18 |
Family
ID=31103447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16954286U Pending JPS6374800U (en) | 1986-11-06 | 1986-11-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6374800U (en) |
-
1986
- 1986-11-06 JP JP16954286U patent/JPS6374800U/ja active Pending
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