JPH02119745U - - Google Patents
Info
- Publication number
- JPH02119745U JPH02119745U JP2840389U JP2840389U JPH02119745U JP H02119745 U JPH02119745 U JP H02119745U JP 2840389 U JP2840389 U JP 2840389U JP 2840389 U JP2840389 U JP 2840389U JP H02119745 U JPH02119745 U JP H02119745U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- memory
- parity
- signal
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図はこの考案の一実施例によるメモリ回路
のブロツク図、第２図は４ビツトバイナリカウン
タを用いた場合のカウント方式の説明図、第３図
は従来のメモリ回路のブロツク図である。
図において、１はメモリ部、２はパリテイ発生
部、３はパリテイ検出部、４はカウント部、５は
アドレス信号、５２は入力データ信号、５３は入
力パリテイビツト信号、５４は制御信号、５５は
出力パリテイビツト信号、５６は出力データ信号
、５７はパリテイエラー信号、５８はメモリ切替
信号、１０１〜１０４はメモリ部１のメモリマツ
プで１０１は“００”のエリア、１０２は“０１
”のエリア、１０３は“０１”のエリア、１０４
は“１１”のエリアである。なお、図中、同一符
号は同一、又は相当部分を示す。
FIG. 1 is a block diagram of a memory circuit according to an embodiment of this invention, FIG. 2 is an explanatory diagram of a counting method using a 4-bit binary counter, and FIG. 3 is a block diagram of a conventional memory circuit. In the figure, 1 is a memory section, 2 is a parity generation section, 3 is a parity detection section, 4 is a count section, 5 is an address signal, 52 is an input data signal, 53 is an input parity bit signal, 54 is a control signal, and 55 is an output Parity bit signal, 56 is output data signal, 57 is parity error signal, 58 is memory switching signal, 101 to 104 are memory map of memory section 1, 101 is "00" area, 102 is "01"
” area, 103 is the “01” area, 104
is the area “11”. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
いる回路において、パリテイエラー信号をカウン
トするカウンタを設け、このカウンタの出力信号
をメモリ部のアドレスにフイードバツクさせたこ
とを特徴とするメモリ回路。 1. A memory circuit in which a parity check is performed by hardware, comprising a counter for counting parity error signals, and an output signal of the counter is fed back to an address in a memory section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2840389U JPH02119745U (en) | 1989-03-13 | 1989-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2840389U JPH02119745U (en) | 1989-03-13 | 1989-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02119745U true JPH02119745U (en) | 1990-09-27 |
Family
ID=31251737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2840389U Pending JPH02119745U (en) | 1989-03-13 | 1989-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02119745U (en) |
-
1989
- 1989-03-13 JP JP2840389U patent/JPH02119745U/ja active Pending
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