JPS6183346U - - Google Patents
Info
- Publication number
- JPS6183346U JPS6183346U JP16773284U JP16773284U JPS6183346U JP S6183346 U JPS6183346 U JP S6183346U JP 16773284 U JP16773284 U JP 16773284U JP 16773284 U JP16773284 U JP 16773284U JP S6183346 U JPS6183346 U JP S6183346U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- serial data
- output
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Correction Of Errors (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
は従来のパリテイ・チエツクビツト発生回路を示
す図である。
図において１は情報ビツトのシリアル・データ
、２はシフト・クロツク、３はパリテイ・チエツ
クビツト信号、４１〜４ｎはエクシクルーシブ・
オア・ゲート、５は奇数パリテイか偶数パリテイ
かを決定する信号、６はシフト・レジスタ、７ａ
〜７ｂはフリツプ・フロツプ、８はエクシクルー
シブ・オア・ゲート、９はシフト・クロツク２に
対して位相遅れをもつクロツク、１０はセツトま
たはリセツト信号１、１１はセツトまたはリセツ
ト信号２である。なお、図中同一あるいは相当部
分には同一符号を付して示してある。
FIG. 1 shows an embodiment of this invention, and FIG. 2 shows a conventional parity check bit generating circuit. In the figure, 1 is information bit serial data, 2 is a shift clock, 3 is a parity check bit signal, and 4 1 to 4n are exclusive bits.
OR gate, 5 is a signal that determines odd parity or even parity, 6 is a shift register, 7a
7b is a flip-flop, 8 is an exclusive OR gate, 9 is a clock with a phase lag with respect to the shift clock 2, 10 is a set or reset signal 1, and 11 is a set or reset signal 2. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.
Claims (1)
記シリアル・データを読み込むためのシフト・ク
ロツクを入力する第１のフリツプ・フロツプと、
上記シフト・クロツクに対し位相遅れをもつクロ
ツクを入力する第２のフリツプ・フロツプと、第
１のフリツプ・フロツプの出力と第２のフリツプ
・フロツプの出力を入力し、第２のフリツプ・フ
ロツプの入力へ出力するエクシクルーシブ・オア
・ゲートからなるパリテイ・チエツクビツト発生
回路。 a first flip-flop for inputting serial data composed of information bits and a shift clock for reading the serial data;
A second flip-flop inputs a clock having a phase delay with respect to the shift clock, and a second flip-flop inputs the output of the first flip-flop and the output of the second flip-flop. A parity check bit generation circuit consisting of an exclusive OR gate that outputs to the input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16773284U JPS6183346U (en) | 1984-11-05 | 1984-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16773284U JPS6183346U (en) | 1984-11-05 | 1984-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183346U true JPS6183346U (en) | 1986-06-02 |
Family
ID=30725521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16773284U Pending JPS6183346U (en) | 1984-11-05 | 1984-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183346U (en) |
-
1984
- 1984-11-05 JP JP16773284U patent/JPS6183346U/ja active Pending
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